From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 103DDC433EF for ; Thu, 10 Feb 2022 10:32:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BB5310E7CB; Thu, 10 Feb 2022 10:32:02 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2748210E7CB; Thu, 10 Feb 2022 10:32:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644489122; x=1676025122; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=aUoUIvaP0mKqGQFmuLEycrw4C0O3v4YsV66X2+0pIe8=; b=h35QXIFWEreuRHj23y9YZlst2k4d1h9wsxNspuuDIXVgrdX//2PWbMhB A6E26guMKuTKEePkNJh1p7nfGFqzWuOnbVF6QSpxHDgOqIfTqBjn9//oN F0OZOtqmRqo+oB0Nsnex4BpUVNgZlYbhh3G5l3SivBhMjFacGYBemnHFy 3FvQx/y2g/JhawHbdZH/LPtG8ldeabyYafQ2KkLLdOpBnGroImgFzvlsx JhkImOiGjFvYVy1MKr4OGiIxrfHrCFMbC2CUxtdNlF8Ug8ChuDljsV3qn 5sXmha5h0sHTlO2Q0pFQI0rRB+fI/KRryg+t9XBjzzUBIn/+/lReR1eDs g==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="233023666" X-IronPort-AV: E=Sophos;i="5.88,358,1635231600"; d="scan'208";a="233023666" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 02:32:01 -0800 X-IronPort-AV: E=Sophos;i="5.88,358,1635231600"; d="scan'208";a="485636297" Received: from scurtin-mobl1.ger.corp.intel.com (HELO [10.213.201.86]) ([10.213.201.86]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 02:31:59 -0800 Message-ID: <1e4fec89-7314-cc7a-db0b-37a1afddec83@linux.intel.com> Date: Thu, 10 Feb 2022 10:31:57 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Michael Cheng , intel-gfx@lists.freedesktop.org References: <20220210012617.1061641-1-michael.cheng@intel.com> <20220210012617.1061641-2-michael.cheng@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: <20220210012617.1061641-2-michael.cheng@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 10/02/2022 01:26, Michael Cheng wrote: > Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc > performs a flush by first performing a clean, follow by an invalidation > operation. > > v2 (Michael Cheng): Use correct macro for cleaning and invalidation the > dcache. > > v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h > > v4 (Michael Cheng): Rebase > > Signed-off-by: Michael Cheng > --- > drivers/gpu/drm/drm_cache.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c > index 66597e411764..ec8d91b088ff 100644 > --- a/drivers/gpu/drm/drm_cache.c > +++ b/drivers/gpu/drm/drm_cache.c > @@ -28,6 +28,7 @@ > * Authors: Thomas Hellström > */ > > +#include I thought linux/cacheflush.h would be correct. Regards, Tvrtko > #include > #include > #include > @@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) > > if (wbinvd_on_all_cpus()) > pr_err("Timed out waiting for cache flush\n"); > + > +#elif defined(CONFIG_ARM64) > + void *end = addr + length; > + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); > #else > WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); > #endif