From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Renninger Subject: Re: [Intel-gfx] less load less performance Date: Tue, 2 Nov 2010 16:53:35 +0100 Message-ID: <201011021653.35823.trenn@suse.de> References: <1288543487.17727.29.camel@zwerg> <20101031191843.GA9292@rhlx01.hs-esslingen.de> <1288554267.31411.14.camel@zwerg> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1288554267.31411.14.camel@zwerg> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: power-bounces-072X8lT/F9NAfugRpC6u6w@public.gmane.org Errors-To: power-bounces-072X8lT/F9NAfugRpC6u6w@public.gmane.org To: power-072X8lT/F9NAfugRpC6u6w@public.gmane.org Cc: Peter Clifton , "intel-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" List-Id: intel-gfx@lists.freedesktop.org On Sunday 31 October 2010 20:44:27 Alexey Fisher wrote: > Am Sonntag, den 31.10.2010, 20:18 +0100 schrieb Andreas Mohr: ... > > > > Why painfully compile a custom c app to keep the CPU busy? > > > > Boot with processor.max_cstate=1 > > Much better performance? --> "BUG"! > > ("BUG" == "something should probably be done about these power management side > > effects") > > for some reasons "processor.max_cstate=1" do not make any difference, > cpu still use C4. This is because the new intel_idle driver is used: cat /sys/devices/system/cpu/cpuidle/current_driver either you pass both: intel_idle.max_cstate=0 processor.max_cstate=1 or with the patch I posted today to the linux-acpi list, idle=halt (C1) idle=poll (busy idling, no power saving at all) can be used: [PATCH] intel_idle: Do not load if user overrides idle function via idle= boot param Hmm, a more generic cpuidle param: cpuidle.max_state= may make sense as well. > Interesting is maxcpus=1 do difference, C4 is used and > it perform good too. I am not familiar with the very details of Atoms very deep C-state implementation, but it could be that all cores/siblings of a CPU socket need to request sleep states so that C4 or whatever HW triggered internal power savings take place. > So what can it be? Some SMP scheduler problem, IRQ > balancing? > I know intel CPUs had some PM problem, if 1 core is disabled it consume > more power (may be no C4?). Sounds like this is the case... Thomas