From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: render p-state support for Sandybridge Date: Fri, 10 Dec 2010 09:46:45 -0800 Message-ID: <20101210094645.1d76cef6@jbarnes-desktop> References: <20101209150046.23bef984@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy2-pub.bluehost.com (oproxy2-pub.bluehost.com [67.222.39.60]) by gabe.freedesktop.org (Postfix) with SMTP id 8375E9E740 for ; Fri, 10 Dec 2010 09:46:51 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 10 Dec 2010 09:37:00 +0000 Chris Wilson wrote: > On Thu, 9 Dec 2010 15:00:46 -0800, Jesse Barnes wrote: > > Note: this patch is just for comments/testing, it should not be > > integrated at this time. > > So that's what drps stands for: dynamic render P-states! Jesse, at the > very least shouldn't we apply the s/HAS_PCH_SPLIT/IS_GEN5/ in order not > to be poking gen5 registers on gen6? > -Chris Or add an IS_IRONLAKE macro; that's what I was really looking for. Will fix. -- Jesse Barnes, Intel Open Source Technology Center