From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: disable rc6 on Cantiga and Crestline Date: Mon, 27 Dec 2010 11:29:04 -0800 Message-ID: <20101227112904.25a65733@jbarnes-desktop> References: <1293251374-2565-1-git-send-email-jbarnes@virtuousgeek.org> <0d30dc$kil0gl@orsmga001.jf.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy2-pub.bluehost.com (oproxy2-pub.bluehost.com [67.222.39.60]) by gabe.freedesktop.org (Postfix) with SMTP id 04BAD9E778 for ; Mon, 27 Dec 2010 11:29:08 -0800 (PST) In-Reply-To: <0d30dc$kil0gl@orsmga001.jf.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, 25 Dec 2010 12:37:52 +0000 Chris Wilson wrote: > On Fri, 24 Dec 2010 20:29:34 -0800, Jesse Barnes wrote: > > The Ironlake code won't work on these old chips, so disable it to avoid > > hanging older systems. > > But AFAICS, pwrctxa is enabled for crestline/cantiga. Any info on whether > that's true? Looking at this some more, we don't have a way of checking whether we're in RC6 on Cantiga. All the regs appear to be programmed correctly to allow it, but the bits indicating current RS state on Ironlake are undefined on Cantiga (and read as 0 on my system). Running the MI_SET_CONTEXT code on Cantiga results in a hang. I don't know why though, even after removing the MI_SUSPEND_FLUSH instructions (which is only available on ILK+) and reducing the command count it hangs at load. Without getting that working and measuring the before/after power, I don't think we can safely enable RC6 on anything before Ironlake. -- Jesse Barnes, Intel Open Source Technology Center