From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yuanhan Liu Subject: Re: [PATCH] drm/i915: make DP training try a little harder Date: Wed, 5 Jan 2011 15:52:39 +0800 Message-ID: <20110105075239.GA2702@yliu-dev.sh.intel.com> References: <1294170794-5334-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B32C9E710 for ; Tue, 4 Jan 2011 23:56:06 -0800 (PST) Content-Disposition: inline In-Reply-To: <1294170794-5334-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jan 04, 2011 at 11:53:14AM -0800, Jesse Barnes wrote: > When trying to do channel equalization, we need to make sure we still > have clock recovery on all lanes while training. We also need to try > clock recovery again if we lose the clock or if channel eq fails 5 > times. We'll try clock recovery up to 5 more times before giving up > entirely. > > Gets suspend/resume working on my Vaio again and brings us back into > compliance with the DP training sequence spec. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_dp.c | 25 ++++++++++++++++++++++--- > 1 files changed, 22 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 1dc6040..35152cb 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1334,12 +1334,13 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) > struct drm_device *dev = intel_dp->base.base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > bool channel_eq = false; > - int tries; > + int tries, cr_tries; > u32 reg; > uint32_t DP = intel_dp->DP; > > /* channel equalization */ > tries = 0; > + cr_tries = 0; > channel_eq = false; > for (;;) { > /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ > @@ -1367,18 +1368,36 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) > if (!intel_dp_get_link_status(intel_dp)) > break; > > + /* Make sure clock is still ok */ > + if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { > + intel_dp_start_link_train(intel_dp); > + cr_tries++; > + continue; > + } > + Hi Jesse, This will cause a endless loop when the clock recovery phase always failed, just like what happend on my test machine. And, FYI, the two patch would not fix bug https://bugs.freedesktop.org/show_bug.cgi?id=32539 the train link still failed. Thanks, Yuanhan Liu > if (intel_channel_eq_ok(intel_dp)) { > channel_eq = true; > break; > } > > - /* Try 5 times */ > - if (tries > 5) > + /* Try 5 times, then try clock recovery if that fails */ > + if (tries > 5) { > + intel_dp_link_down(intel_dp); > + intel_dp_start_link_train(intel_dp); > + tries = 0; > + cr_tries++; > break; > + } > > /* Compute new intel_dp->train_set as requested by target */ > intel_get_adjust_train(intel_dp); > ++tries; > + > + if (cr_tries > 5) { > + DRM_ERROR("failed to train DP, aborting\n"); > + intel_dp_link_down(intel_dp); > + break; > + } > } > > if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) > -- > 1.7.0.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx