From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 2/2] drm/i915: add Ivy Bridge page flip support Date: Tue, 14 Jun 2011 12:35:10 -0700 Message-ID: <20110614123510.5ae559a2@jbarnes-desktop> References: <1308075188-2821-1-git-send-email-jbarnes@virtuousgeek.org> <1308075188-2821-2-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id E0692A08A5 for ; Tue, 14 Jun 2011 12:35:13 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 14 Jun 2011 19:22:33 +0100 Chris Wilson wrote: > On Tue, 14 Jun 2011 11:13:08 -0700, Jesse Barnes wrote: > > Use the blit ring for submitting flips since the render ring doesn't > > generate flip complete interrupts. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++ > > 1 files changed, 25 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 06748f3a..3d095de 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -6379,6 +6379,28 @@ out: > > return ret; > > } > > > > +static int intel_gen7_queue_flip(struct drm_device *dev, > > + struct drm_crtc *crtc, > > + struct drm_framebuffer *fb, > > + struct drm_i915_gem_object *obj) > > +{ > > + struct drm_i915_private *dev_priv = dev->dev_private; > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; > > + int ret; > > + > > + ret = intel_ring_begin(&dev_priv->ring[BCS], 4); > > + if (ret) > > + goto out; > > + > > + intel_ring_emit(&dev_priv->ring[BCS], (MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)) | (1 << 17)); > What's the magic number? 80 column limit? > -Chris All good points. See the updated patches. Thanks, -- Jesse Barnes, Intel Open Source Technology Center