From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [RFC PATCH] drm/i915/dp: Dither down to 6bpc if it makes the mode fit Date: Fri, 22 Jul 2011 11:57:13 -0700 Message-ID: <20110722115713.4aeee200@jbarnes-desktop> References: <1311174531-23070-1-git-send-email-ajax@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id C5D089E740 for ; Fri, 22 Jul 2011 11:57:19 -0700 (PDT) In-Reply-To: <1311174531-23070-1-git-send-email-ajax@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Adam Jackson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 20 Jul 2011 11:08:51 -0400 Adam Jackson wrote: > Some active adaptors (VGA usually) only have two lanes at 2.7GHz. > That's a maximum pixel clock of 144MHz at 8bpc, but 192MHz at 6bpc. > > Signed-off-by: Adam Jackson > --- > > Patch is against drm-intel-next. Not even compile-tested yet, just > looking for feedback. I _think_ the pre-gen5 path is right, the GM45 doc > makes it sound like the bpc and dither bits only affect DP. Yeah, it would be good to have this. > + /* default to 8bpc */ > + pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); > + if (is_dp) { > + if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { > + pipeconf |= PIPECONF_BPP_6 | > + PIPECONF_DITHER_EN | > + PIPECONF_DITHER_TYPE_ST1; > + } > + } > + > dpll |= DPLL_VCO_ENABLE; Maybe this part would be cleaner if you added G4x support to choose_pipe_bpp_dither and called it here instead? -- Jesse Barnes, Intel Open Source Technology Center