From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time Date: Fri, 12 Aug 2011 15:18:09 -0700 Message-ID: <20110812151809.7fdab276@jbarnes-desktop> References: <1313186133-2724-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy4-pub.bluehost.com (oproxy4-pub.bluehost.com [69.89.21.11]) by gabe.freedesktop.org (Postfix) with SMTP id 578219EDD5 for ; Fri, 12 Aug 2011 15:18:24 -0700 (PDT) Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.76) (envelope-from ) id 1Qs03b-0000ts-Kw for intel-gfx@lists.freedesktop.org; Fri, 12 Aug 2011 16:18:23 -0600 In-Reply-To: <1313186133-2724-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 12 Aug 2011 14:55:32 -0700 Jesse Barnes wrote: > GFX_MODE controls important behavior like PPGTT, run lists, and TLB > invalidate behavior. On the SDV I'm using, the TLB invalidation mode > was defaulting to "pipe control only" which meant regular MI_FLUSHes > wouldn't actually flush the TLB, leading to all sorts of stale data > getting used. > > So initialize it to 0 at ring buffer init time until we actually use > PIPE_CONTROL for TLB invalidation. Ignore this one, see below for an updated patch that uses bit definitions and makes sure the register gets reset at GPU reset time as well. -- Jesse Barnes, Intel Open Source Technology Center >>From ac1b88dc2f4cd3a00746063899c6e6be4d5f2065 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 12 Aug 2011 15:15:06 -0700 Subject: [PATCH] drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that MI_FLUSH would flush the TLBs in addition to the rest of the caches indicated in the MI_FLUSH command. However starting with Ivybridge, the register defaults to 0x2800 out of reset, meaning that to invalidate the TLB we need to use PIPE_CONTROL. Since we're not doing that yet, go back to the old default so things work. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7033e01..26641ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -375,6 +375,7 @@ # define MI_FLUSH_ENABLE (1 << 11) #define GFX_MODE 0x02520 +#define GFX_MODE_GEN7 0x0229c #define GFX_RUN_LIST_ENABLE (1<<15) #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) #define GFX_SURFACE_FAULT_ENABLE (1<<12) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 47b9b27..6dad947 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -290,6 +290,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (IS_GEN6(dev) || IS_GEN7(dev)) mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; I915_WRITE(MI_MODE, mode); + if (IS_GEN7(dev)) + I915_WRITE(GFX_MODE_GEN7, (GFX_REPLAY_MODE << 16) | + GFX_REPLAY_MODE); } if (INTEL_INFO(dev)->gen >= 6) { -- 1.7.4.1