From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on
 gen6+.
Date: Mon, 26 Sep 2011 22:31:56 +0200
Message-ID: <20110926203156.GE2804@phenom.ffwll.local>
References: <1317063563-1526-1-git-send-email-kenneth@whitecape.org>
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To: Kenneth Graunke <kenneth@whitecape.org>
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On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote:
> +static int
> +gen6_render_ring_flush(struct intel_ring_buffer *ring,
> +                         u32 invalidate_domains, u32 flush_domains)
> +{
> +	u32 flags = 0;
> +	struct pipe_control *pc = ring->private;
> +	u32 scratch_addr = pc->gtt_offset + 128;
> +	int ret;
> +
> +	/* Force SNB workarounds for PIPE_CONTROL flushes */
> +	intel_emit_post_sync_nonzero_flush(ring);
> +
> +	/* Just flush everything for now */
> +	flags |= PIPE_CONTROL_WC_FLUSH;
> +	flags |= PIPE_CONTROL_IS_FLUSH;
> +	flags |= PIPE_CONTROL_TC_FLUSH;
> +	flags |= PIPE_CONTROL_DEPTH_FLUSH;
> +	flags |= PIPE_CONTROL_VFC;

Any reason you're not also setting the constant cache and state cache
invalidate bits?
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48