From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+. Date: Mon, 3 Oct 2011 14:21:39 -0700 Message-ID: <20111003142139.52bf7357@jbarnes-desktop> References: <1317063563-1526-1-git-send-email-kenneth@whitecape.org> <20111003130016.61bcc8c0@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy5-pub.bluehost.com (oproxy5-pub.bluehost.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id 0CA7FA0926 for ; Mon, 3 Oct 2011 14:21:49 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Keith Packard Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 03 Oct 2011 14:14:53 -0700 Keith Packard wrote: > On Mon, 3 Oct 2011 13:00:16 -0700, Jesse Barnes wrote: > > > This is the only bit I'd like to see changed. While we still have the > > domain tracking code we may as well try to honor it and limit our > > flushing here like we do with MI_FLUSH. > > I'd like to see this patch put in place, and then any 'optimization' > added afterwards so we can avoid having to revert this change when it > breaks. Sounds good. I guess Ken needs to re-post anyway to add the two extra bits... -- Jesse Barnes, Intel Open Source Technology Center