From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 2/3] i915: Rename PIPE_CONTROL bit defines to be less terse. Date: Wed, 5 Oct 2011 15:29:25 -0700 Message-ID: <20111005222924.GA10841@seagal.amr.corp.intel.com> References: <1317708160-1761-1-git-send-email-kenneth@whitecape.org> <1317708160-1761-2-git-send-email-kenneth@whitecape.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 444AD9E75E for ; Wed, 5 Oct 2011 15:29:43 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1317708160-1761-2-git-send-email-kenneth@whitecape.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Kenneth Graunke Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Oct 03, 2011 at 11:02:39PM -0700, Kenneth Graunke wrote: > "STALL_AT_SCOREBOARD" is much clearer than "STALL_EN" now that there are > several different kinds of stalls. Also, "INSTRUCTION_CACHE_FLUSH" is a > lot easier to understand at a glance than the terse "IS_FLUSH." > > Signed-off-by: Kenneth Graunke > --- > drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++-------- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++-- > 2 files changed, 12 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d691781..bfe8488 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -243,15 +243,15 @@ > #define DISPLAY_PLANE_A (0<<20) > #define DISPLAY_PLANE_B (1<<20) > #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)) > -#define PIPE_CONTROL_QW_WRITE (1<<14) > -#define PIPE_CONTROL_DEPTH_STALL (1<<13) > -#define PIPE_CONTROL_WC_FLUSH (1<<12) > -#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ > -#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ > -#define PIPE_CONTROL_ISP_DIS (1<<9) > -#define PIPE_CONTROL_NOTIFY (1<<8) > +#define PIPE_CONTROL_QW_WRITE (1<<14) > +#define PIPE_CONTROL_DEPTH_STALL (1<<13) > +#define PIPE_CONTROL_WRITE_FLUSH (1<<12) > +#define PIPE_CONTROL_INSTRUCTION_CACHE_FLUSH (1<<11) /* MBZ on Ironlake */ > +#define PIPE_CONTROL_TEXTURE_CACHE_FLUSH (1<<10) /* GM45+ only */ > +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) > +#define PIPE_CONTROL_NOTIFY (1<<8) > +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ > -#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ What does "write flush" mean? At least for Gen6+: #define PIPE_CONTROL_RENDER_CACHE_FLUSH (1<<12) If this is invalid before Ironlake, let's change the comment, otherwise ignore. #define PIPE_CONTROL_INSTRUCTION_CACHE_FLUSH (1<<11) /* Gen6+ */ Ben