From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on
	gen6+.
Date: Sun, 16 Oct 2011 18:27:55 -0700
Message-ID: <20111016182755.7909f0ff@bwidawsk.net>
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To: Daniel Vetter <daniel.vetter@ffwll.ch>
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On Sun, 16 Oct 2011 10:23:31 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> From: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> v2 by danvet: Use a new flag to flush the render target cache on gen6+
> (hw reuses the old write flush bit), as suggested by Ben Widawsdy.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> [danvet: this seems to fix cairo-perf-trace hangs on my snb]
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>