From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 1/3] drm/i915: Ivybridge still has fences! Date: Sun, 23 Oct 2011 14:09:07 +0200 Message-ID: <20111023120907.GG2953@phenom.ffwll.local> References: <1318189923-4609-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ww0-f43.google.com (mail-ww0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 590509E76C for ; Sun, 23 Oct 2011 05:08:17 -0700 (PDT) Received: by wwf10 with SMTP id 10so6231174wwf.12 for ; Sun, 23 Oct 2011 05:08:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , Keith Packard Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, stable@kernel.org List-Id: intel-gfx@lists.freedesktop.org On Sun, Oct 23, 2011 at 12:23:14PM +0100, Chris Wilson wrote: > Regardless of the outcome of Jesse's request for an if-ladder, the > substance of the patches look sound. > > However, I remain unconvinced that there are 32 fence registers on IVB. > Daniel's evidence is based upon the size of the register map (and not > on the BSPEC explicitly stating a change to 32 ;-), but most tellingly > the bitfields for fence-number in other registers have not been updated - > so we can only safely allocated the first 16 anyway... > (For instance, FBC_CTL). Ok, I've rechecked bspec. The FBC_CTL fence number is indeed only 4 bits wide, but on snb+ is must be written as 0. The cpu fence stuff for fbc moved to DPFC_CONTROL_SA, which has room enough for 5 bits. Unfortunately bspec is silent on whether that has actually grown from 4 bits for ivb. On a future hw iteration I'm not really allowed to talk about it is all correctly in place (i.e. bspec definitions for all 32 fence regs plus the 5 bit wide fence number in DPFC_CTL_SA). So I think I'll drop this patch till things clear up. Keith, can take a look at patches 1-2 and consider merging them for 3.2? Yours, Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48