From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+) Date: Wed, 7 Dec 2011 10:38:41 -0800 Message-ID: <20111207103841.7627b5fe@jbarnes-desktop> References: <1319337685-26195-1-git-send-email-ben@bwidawsk.net> <1319337685-26195-2-git-send-email-ben@bwidawsk.net> <87fwgwfcvy.fsf@eliezer.anholt.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0183152667==" Return-path: Received: from oproxy3-pub.bluehost.com (oproxy3-pub.bluehost.com [69.89.21.8]) by gabe.freedesktop.org (Postfix) with SMTP id 1BF329F0BD for ; Wed, 7 Dec 2011 10:38:47 -0800 (PST) In-Reply-To: <87fwgwfcvy.fsf@eliezer.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: Ben Widawsky , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0183152667== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/d2VEzq8WiQaPJGxnVuwiSf/"; protocol="application/pgp-signature" --Sig_/d2VEzq8WiQaPJGxnVuwiSf/ Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Wed, 07 Dec 2011 10:35:45 -0800 Eric Anholt wrote: > On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky wrote: > > The docs say this is required for Gen7, and since the bit was added for > > Gen6, we are also setting it there pit pf paranoia. Particularly as > > Chris points out, if PIPE_CONTROL counts as a 3d state packet. > >=20 > > This was found through doc inspection by Ken and applies to Gen6+; > >=20 > > Cc: Keith Packard > > Reported-by: Kenneth Graunke > > Signed-off-by: Ben Widawsky > > Reviewed-by: Chris Wilson > > Reviewed-by: Daniel Vetter >=20 > Reviewed-by: Eric Anholt >=20 > however, it doesn't appear to help Ivybridge IRQ troubles. You could try something like the below to force the use of PIPE_NOTIFY instead. Only lightly tested on IVB when we had lots of other bugs, so I'm not sure if it works at all. --=20 Jesse Barnes, Intel Open Source Technology Center diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_dr= v.c index 60e4b9e..ce045a8 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -62,7 +62,7 @@ module_param_named(semaphores, i915_semaphores, int, 0600= ); MODULE_PARM_DESC(semaphores, "Use semaphores for inter-ring sync (default: false)"); =20 -unsigned int i915_enable_rc6 __read_mostly =3D 1; +unsigned int i915_enable_rc6 __read_mostly =3D 0; module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); MODULE_PARM_DESC(i915_enable_rc6, "Enable power-saving render C-state 6 (default: true)"); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_ir= q.c index 02f96fd..4ab2e90 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -568,7 +568,7 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) atomic_inc(&dev_priv->irq_received); =20 if (IS_GEN6(dev)) - bsd_usr_interrupt =3D GT_GEN6_BSD_USER_INTERRUPT; + bsd_usr_interrupt =3D GT_GEN6_BSD_USER_INTERRUPT | GT_PIPE_NOTIFY; =20 /* disable master interrupt before clearing iir */ de_ier =3D I915_READ(DEIER); @@ -602,7 +602,7 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) notify_ring(dev, &dev_priv->ring[RCS]); if (gt_iir & bsd_usr_interrupt) notify_ring(dev, &dev_priv->ring[VCS]); - if (gt_iir & GT_BLT_USER_INTERRUPT) + if (gt_iir & (GT_BLT_USER_INTERRUPT | GT_PIPE_NOTIFY)) notify_ring(dev, &dev_priv->ring[BCS]); =20 if (de_iir & DE_GSE) @@ -1810,7 +1810,8 @@ static int ironlake_irq_postinstall(struct drm_device= *dev) render_irqs =3D GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | - GT_BLT_USER_INTERRUPT; + GT_BLT_USER_INTERRUPT | + GT_PIPE_NOTIFY; else render_irqs =3D GT_USER_INTERRUPT | diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915= /intel_ringbuffer.c index 47b9b27..0a67334 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -292,8 +292,7 @@ static int init_render_ring(struct intel_ring_buffer *r= ing) I915_WRITE(MI_MODE, mode); } =20 - if (INTEL_INFO(dev)->gen >=3D 6) { - } else if (IS_GEN5(dev)) { + if (INTEL_INFO(dev)->gen >=3D 5) { ret =3D init_pipe_control(ring); if (ret) return ret; @@ -411,10 +410,13 @@ pc_render_add_request(struct intel_ring_buffer *ring, * incoherence by flushing the 6 PIPE_NOTIFY buffers out to * memory before requesting an interrupt. */ - ret =3D intel_ring_begin(ring, 32); + ret =3D intel_ring_begin(ring, 38); if (ret) return ret; =20 + update_semaphore(ring, 0, seqno); + update_semaphore(ring, 1, seqno); + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); @@ -1289,12 +1291,10 @@ int intel_init_render_ring_buffer(struct drm_device= *dev) struct intel_ring_buffer *ring =3D &dev_priv->ring[RCS]; =20 *ring =3D render_ring; - if (INTEL_INFO(dev)->gen >=3D 6) { - ring->add_request =3D gen6_add_request; + if (INTEL_INFO(dev)->gen >=3D 5) { + ring->add_request =3D pc_render_add_request; ring->irq_get =3D gen6_render_ring_get_irq; ring->irq_put =3D gen6_render_ring_put_irq; - } else if (IS_GEN5(dev)) { - ring->add_request =3D pc_render_add_request; ring->get_seqno =3D pc_render_get_seqno; } =20 --Sig_/d2VEzq8WiQaPJGxnVuwiSf/ Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAEBAgAGBQJO37KxAAoJEIEoDkX4Qk9hEvsP/1+UV5iq565MvVi/v7BAlaez XFTqnZTCsQZOSDnee5fR/2jmEtDmBPjlNFSegsVyV+jmJp0XEJbm5uBCzgK6VKXr wLR7Kwb0jzFy2/fZBT5HQPt/W6a4D8Gs1MEa3y2zQSbTmEc10EVUZsm89Nv80TXj +PoaZ53G/S1FQzC9G9VSOxInwIMh+s1WzU8TwP9W1qtZ22pKK5arzESDHC55sNkK 7/LNm3lWsqvq3RrVMbNsKpMB0CU+ug5MOroPR8TCNickv/7kAEZr3XtZgimSpf0C d8WYi0kQ7CmaEaR27t8hBX8p2KN9mvci6MsVt9gI+wOLn4foVqmUkFkYEeTple4F mN68T0scVSAD0JfWnpJXY0uQD7662/GNlt/Lci1ypa1AoTbVYaxfd6YFHB/xRIKg 9JjYeYqnMd2gToPNMxEWUOM1GqegEFL/oWc1WhhFi146Rd982kJKHjHqbP0cKU9c wo8iOHi6yowhKoiDbKBJJPhaCecg0nSy1ZFQ6YKHI5HM0CBFcntASOPR9BmAfii4 SSKCfZQBrW5TPLXVxqmRKjNx17fx5HrHogm0iYVGqivPvyUj3t02wwh5wFi4pkoh jUtwb/TtfUfUpcboplyxlYxqdMC1xJdgKNinPYDogtAkYtprZe+S8yQZAyf5vsqm 7np6z0yf4m1QDis9zIoj =BHtQ -----END PGP SIGNATURE----- --Sig_/d2VEzq8WiQaPJGxnVuwiSf/-- --===============0183152667== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0183152667==--