From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 2/3] drm/i915: Force sync command ordering (Gen6+) Date: Wed, 14 Dec 2011 13:33:11 -0800 Message-ID: <20111214133311.06ed23ff@jbarnes-desktop> References: <1319337685-26195-1-git-send-email-ben@bwidawsk.net> <1319337685-26195-2-git-send-email-ben@bwidawsk.net> <87fwgwfcvy.fsf@eliezer.anholt.net> <20111207103841.7627b5fe@jbarnes-desktop> <20111207115805.13f5cfde@jbarnes-desktop> <87ty5cf6hc.fsf@eliezer.anholt.net> <20111207130329.1f5fb6c1@jbarnes-desktop> <87y5umxyj7.fsf@eliezer.anholt.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1242343588==" Return-path: Received: from oproxy5-pub.bluehost.com (oproxy5-pub.bluehost.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id C6E159E74C for ; Wed, 14 Dec 2011 13:33:13 -0800 (PST) In-Reply-To: <87y5umxyj7.fsf@eliezer.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: Ben Widawsky , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1242343588== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/znmMfxae81Vm6Xn+xp_N6dM"; protocol="application/pgp-signature" --Sig_/znmMfxae81Vm6Xn+xp_N6dM Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Thu, 08 Dec 2011 18:35:24 -0800 Eric Anholt wrote: > Since MI_FLUSH_DW exists on gen6, and keithp says we still have > outstanding issues with missed blit IRQs there, I started trying it > today. Two kernel branches posted at > git://people.freedesktop.org/~anholt/linux/ >=20 > flush-dw-notify: This is the initial attempt I did with MI_FLUSH_DW with > internal notify. Quickly produced missed blit IRQs. I thought this was > because the notify was in parallel with the post-sync op, not synced to > be after. So I reverted part of the patch and produced... Bummer, that one looks like it ought to work. On current drm-intel-next, this patch seems to be preventing missed IRQs on IVB at least. Anyone else wanna give it a try and confirm? I've only tested with Eric's blit-and-wait.c test so far. --=20 Jesse Barnes, Intel Open Source Technology Center diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_ir= q.c index b40004b..cb821a0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -482,78 +482,83 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); POSTING_READ(DEIER); =20 - de_iir =3D I915_READ(DEIIR); - gt_iir =3D I915_READ(GTIIR); - pch_iir =3D I915_READ(SDEIIR); - pm_iir =3D I915_READ(GEN6_PMIIR); + /* + * Try to mitigate dropped IRQs by handling as many as possible + * each time we get a physical interrupt. + */ + while (1) { + de_iir =3D I915_READ(DEIIR); + gt_iir =3D I915_READ(GTIIR); + pch_iir =3D I915_READ(SDEIIR); + pm_iir =3D I915_READ(GEN6_PMIIR); + + if (de_iir =3D=3D 0 && gt_iir =3D=3D 0 && pch_iir =3D=3D 0 && pm_iir =3D= =3D 0) { + I915_WRITE(DEIER, de_ier); + POSTING_READ(DEIER); + return ret; + } =20 - if (de_iir =3D=3D 0 && gt_iir =3D=3D 0 && pch_iir =3D=3D 0 && pm_iir =3D= =3D 0) - goto done; + ret =3D IRQ_HANDLED; =20 - ret =3D IRQ_HANDLED; + if (dev->primary->master) { + master_priv =3D dev->primary->master->driver_priv; + if (master_priv->sarea_priv) + master_priv->sarea_priv->last_dispatch =3D + READ_BREADCRUMB(dev_priv); + } =20 - if (dev->primary->master) { - master_priv =3D dev->primary->master->driver_priv; - if (master_priv->sarea_priv) - master_priv->sarea_priv->last_dispatch =3D - READ_BREADCRUMB(dev_priv); - } + if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) + notify_ring(dev, &dev_priv->ring[RCS]); + if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) + notify_ring(dev, &dev_priv->ring[VCS]); + if (gt_iir & GT_BLT_USER_INTERRUPT) + notify_ring(dev, &dev_priv->ring[BCS]); =20 - if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) - notify_ring(dev, &dev_priv->ring[RCS]); - if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[VCS]); - if (gt_iir & GT_BLT_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[BCS]); + if (de_iir & DE_GSE_IVB) + intel_opregion_gse_intr(dev); =20 - if (de_iir & DE_GSE_IVB) - intel_opregion_gse_intr(dev); + if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { + intel_prepare_page_flip(dev, 0); + intel_finish_page_flip_plane(dev, 0); + } =20 - if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { - intel_prepare_page_flip(dev, 0); - intel_finish_page_flip_plane(dev, 0); - } + if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { + intel_prepare_page_flip(dev, 1); + intel_finish_page_flip_plane(dev, 1); + } =20 - if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { - intel_prepare_page_flip(dev, 1); - intel_finish_page_flip_plane(dev, 1); - } + if (de_iir & DE_PIPEA_VBLANK_IVB) + drm_handle_vblank(dev, 0); =20 - if (de_iir & DE_PIPEA_VBLANK_IVB) - drm_handle_vblank(dev, 0); + if (de_iir & DE_PIPEB_VBLANK_IVB) + drm_handle_vblank(dev, 1); =20 - if (de_iir & DE_PIPEB_VBLANK_IVB) - drm_handle_vblank(dev, 1); + /* check event from PCH */ + if (de_iir & DE_PCH_EVENT_IVB) { + if (pch_iir & SDE_HOTPLUG_MASK_CPT) + queue_work(dev_priv->wq, + &dev_priv->hotplug_work); + pch_irq_handler(dev); + } =20 - /* check event from PCH */ - if (de_iir & DE_PCH_EVENT_IVB) { - if (pch_iir & SDE_HOTPLUG_MASK_CPT) - queue_work(dev_priv->wq, &dev_priv->hotplug_work); - pch_irq_handler(dev); - } + if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { + unsigned long flags; + spin_lock_irqsave(&dev_priv->rps_lock, flags); + WARN(dev_priv->pm_iir & pm_iir, + "Missed a PM interrupt\n"); + dev_priv->pm_iir |=3D pm_iir; + I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); + POSTING_READ(GEN6_PMIMR); + spin_unlock_irqrestore(&dev_priv->rps_lock, flags); + queue_work(dev_priv->wq, &dev_priv->rps_work); + } =20 - if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { - unsigned long flags; - spin_lock_irqsave(&dev_priv->rps_lock, flags); - WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); - dev_priv->pm_iir |=3D pm_iir; - I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); - POSTING_READ(GEN6_PMIMR); - spin_unlock_irqrestore(&dev_priv->rps_lock, flags); - queue_work(dev_priv->wq, &dev_priv->rps_work); + /* should clear PCH hotplug event before clear CPU irq */ + I915_WRITE(SDEIIR, pch_iir); + I915_WRITE(GTIIR, gt_iir); + I915_WRITE(DEIIR, de_iir); + I915_WRITE(GEN6_PMIIR, pm_iir); } - - /* should clear PCH hotplug event before clear CPU irq */ - I915_WRITE(SDEIIR, pch_iir); - I915_WRITE(GTIIR, gt_iir); - I915_WRITE(DEIIR, de_iir); - I915_WRITE(GEN6_PMIIR, pm_iir); - -done: - I915_WRITE(DEIER, de_ier); - POSTING_READ(DEIER); - - return ret; } =20 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915= /intel_ringbuffer.c index ca70e2f..a9bdcd6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1301,9 +1301,11 @@ gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) static void gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) { +#if 0 return gen6_ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT, GEN6_BSD_USER_INTERRUPT); +#endif } =20 /* ring buffer for Video Codec for Gen6+ */ --Sig_/znmMfxae81Vm6Xn+xp_N6dM Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAEBAgAGBQJO6RYXAAoJEIEoDkX4Qk9h7j0P/RoOtLuSZsrKxUHOZpBvIOvY b4b3VceowYMbTcrzSSSduD3jGtZTa78bcRN0F1UowhlCkQPrsVFUHEakGs+BBwaS Bp/kfKmMqWEIceZdOhLzaroBHdYaCkPx3T2yycx9Yg8hKXKhVPptPyKSjF1kG5dc wT8MqoLbOX6HpwPH53ie5Tcu4rZvidkbS2i3BuuYIUaQzuPAaDS7ClKdX9FNlL8m 8k69GxfVcm33SabQqtvyzRMxW/6WuuU2znD8HgpchadWdCCZoHzJ1jO+qcCOF0Mv EP06Xv9oeimUi++JlyckBD84L/gSS/9QO7idypx+GvF2UNkw7vtHkdbbnNL+3C/i wtKlfs08aUKfY1lezCwPdGtYek37Ndn4UJitx84xWn/n/cG3rYGQc3rFkPyQbWND 9O27veteHOUlgPRN1nP4hRYTKAYSs/a8Bn+lTmzfndYj6IyY/kK74/0dVt7wLUsP HufawhRVImYQK+pm+QsnqGftBEkLCMUIr/jB8HAwIa5EIXaUOXC6qZrOs75miXdt DrExHYVfSlI9/qM7Orz4dGGya2ut7kIqlwonIPt6W84uwSno1rOh7LGIuGfOJTqh S7j9Gjl8KNWpSd6xZZpb7NiGzcEoyeoZTsfx2XOgNwAA6CrztSlqgB0iamZEH9/t o+1qXoYGPePH62em8oph =bBOH -----END PGP SIGNATURE----- --Sig_/znmMfxae81Vm6Xn+xp_N6dM-- --===============1242343588== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1242343588==--