From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: add missing SDVO bits for interlaced modes on ILK Date: Tue, 14 Feb 2012 11:27:49 -0800 Message-ID: <20120214112749.279162d6@jbarnes-desktop> References: <20120210085936.76488e6b@jbarnes-desktop> <1329246430-21453-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0369588063==" Return-path: Received: from oproxy4-pub.bluehost.com (oproxy4-pub.bluehost.com [69.89.21.11]) by gabe.freedesktop.org (Postfix) with SMTP id 5FB8C9E7FF for ; Tue, 14 Feb 2012 11:27:52 -0800 (PST) In-Reply-To: <1329246430-21453-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org --===============0369588063== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/RCM5+siSWZ4S2zmFg/tv0Qr"; protocol="application/pgp-signature" --Sig_/RCM5+siSWZ4S2zmFg/tv0Qr Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Tue, 14 Feb 2012 17:07:09 -0200 Paulo Zanoni wrote: > From: Paulo Zanoni >=20 > This was pointed by Jesse Barnes. The code now seems to follow the > specification but I don't have an SDVO device to really test this. >=20 > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 7 ++++++- > 2 files changed, 7 insertions(+), 1 deletions(-) >=20 > Did someone test interlaced modes with SDVO? >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 5c62b78..52a06be 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3365,6 +3365,7 @@ > #define TRANS_INTERLACE_MASK (7<<21) > #define TRANS_PROGRESSIVE (0<<21) > #define TRANS_INTERLACED (3<<21) > +#define TRANS_LEGACY_INTERLACED_ILK (2<<21) > #define TRANS_8BPC (0<<5) > #define TRANS_10BPC (1<<5) > #define TRANS_6BPC (2<<5) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index db7ccbb..3c8a332 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1267,6 +1267,7 @@ static void intel_enable_transcoder(struct drm_i915= _private *dev_priv, > { > int reg; > u32 val, pipeconf_val; > + struct drm_crtc *crtc =3D dev_priv->pipe_to_crtc_mapping[pipe]; > =20 > /* PCH only available on ILK+ */ > BUG_ON(dev_priv->info->gen < 5); > @@ -1293,7 +1294,11 @@ static void intel_enable_transcoder(struct drm_i91= 5_private *dev_priv, > =20 > val &=3D ~TRANS_INTERLACE_MASK; > if ((pipeconf_val & PIPECONF_INTERLACE_MASK) =3D=3D PIPECONF_INTERLACED= _ILK) > - val |=3D TRANS_INTERLACED; > + if (HAS_PCH_IBX(dev_priv->dev) && > + intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) > + val |=3D TRANS_LEGACY_INTERLACED_ILK; > + else > + val |=3D TRANS_INTERLACED; > else > val |=3D TRANS_PROGRESSIVE; > =20 Yep, looks correct. Thanks Paulo. Reviewed-by: Jesse Barnes --=20 Jesse Barnes, Intel Open Source Technology Center --Sig_/RCM5+siSWZ4S2zmFg/tv0Qr Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPOrW1AAoJEIEoDkX4Qk9hNE0P/3fuQDoc+qyM2nbiFpsBT8WJ Il/7UzVwIS/F2sxLWgmEJYZVcVC0oT+brzdOE0ATrhmNh1OvewNYlErzl+hmW783 d/zo1O+TlMY31P8OgiAAz1f2krUqZcaifIUSZFh2gH30ehs/IQ/a6dXKojyq6FGq is4j0pJDg0m5AVQVjaTZ1jw0FTWyq8weAoeIe726uuzMkTZXyeUBQ91exWQaZxqH pxFL9ORArCSTOs6niqwaxAqjM7M+9/Zsbkyr/95w1wBdiyEqmwvy9e4WzQ56iR6n aF96QvJM0iiNgzXLtMR6YoHWRzi5GGpIEJ/OSi0YqVnWFGaq46TYIFbekWHwcc+d /20Ur9PoWLWUQNOg6Pt2buejfCytPP842fpnxocsYKdAg9IDYqUQq387+n7mMKzn /quYpXjsMoAcuXyGqtyLNGRPAI3fb+iA3srDeYUdhi5XMDquXIQzBZ6kcgkFwoLo tM9hIDtrlqFrWR7T1yCS+yv5XnyjSe6adxIibouzJme9ZJ+0jLKP+k1F9ZI1LPLl bPOR/47Dkv4Xr+nJmEpCDhfJO2Jj+HeGdSLMuXPv6dMwBFwRDCbfKTl3S0E/pXiv tv16MwYeVi9Q8MpfwLv3vODQsLWN9RI5MAXF/rSOBmxjwCj4KkgUZToC0WWvsOw/ A+iWWZhtioKoGIJw9YP9 =oETh -----END PGP SIGNATURE----- --Sig_/RCM5+siSWZ4S2zmFg/tv0Qr-- --===============0369588063== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0369588063==--