From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions Date: Wed, 21 Mar 2012 15:11:49 -0700 Message-ID: <20120321151149.4902adff@jbarnes-desktop> References: <1332359326-15051-1-git-send-email-jbarnes@virtuousgeek.org> <1332359326-15051-17-git-send-email-jbarnes@virtuousgeek.org> <20120321211125.GH9913@phenom.ffwll.local> <20120321143220.71b94d63@jbarnes-desktop> <1332366958.10513.127.camel@atropine> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0719400081==" Return-path: Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by gabe.freedesktop.org (Postfix) with SMTP id 941A19E761 for ; Wed, 21 Mar 2012 15:11:52 -0700 (PDT) In-Reply-To: <1332366958.10513.127.camel@atropine> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Adam Jackson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0719400081== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/+lykwUW3s=J_mz92qvd4V0v"; protocol="application/pgp-signature" --Sig_/+lykwUW3s=J_mz92qvd4V0v Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Wed, 21 Mar 2012 17:55:58 -0400 Adam Jackson wrote: > On Wed, 2012-03-21 at 14:32 -0700, Jesse Barnes wrote: >=20 > > We need force wake, just not for any parts I've tested yet (the early > > ones had the Punit disabled). > >=20 > > This code adheres to the spec, but I'll need a part with the Punit > > enabled in order to test & verify. Until then we can leave it disabled. >=20 > Can we consider Gunit and Punit to be roughly the analogues of GPU and > PCH? Just trying to make sure I know what all the nouns mean. No it's really a sub-component, smaller than either of those. It's responsible for binding together the GT core, the display, and the memory interface. It exposes some regs in the PCI BAR (rudely shoving aside the display ones) for doing things like forcewake, turbo, and tlb flushing, along with top level interrupt handling. --=20 Jesse Barnes, Intel Open Source Technology Center --Sig_/+lykwUW3s=J_mz92qvd4V0v Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPalIlAAoJEIEoDkX4Qk9hvyUP/3HwsFqBlMK1eDdQiycl/p/A sD+0TS6FPBV2emP1TB/mkAKDQuWyuKQb2Ek1jOSsR8Y8xIZAoXr0ku/blJ7g2/+2 wwH89OeByRXEb0YKjG6eYj1RkscqkKoucuuAESvAp2FcqAWJ8DMOX0u2cc08OAyB gtm9uuFbRRtCE/4IDmv8Y2ECsja3VDj5CtT0KDZwbZaMisAgkbYvuiEY0gLcB/p1 tK45HAbQdZ4AS2sYhosF/RF4RaNU+7CxkAqdl/IWX8+MK0uo1Z/g2kaKCK9UDtLX CzOOBnXk19ePsOwcRBVZ4riamz7AAtcxDod2X6N7j+0EcgYK/8zaOoPTD+lU1wPz LqcZxEXiD1Auq1H+2UkFmropdF3cxKJTo8fKk4HGMp+hCPbHQQKofvvEkyv/9t/n ZwwLu5BOEkkMdyr2n9ZexMcvYpx8INuVQPmSohgSG4vrOfuw3hfY6gD+ILYTsyMy npkUBjOiPojNAzz8iJDSS3jDMw4DiKd0Z+IO4Ohp6Gg9d5jACb5gfX7zES/YR4wH yFn3bVrKfEejNIIgKH0mnR80mJEmpFlJ1e/QkjFsPCYVZzo5LkDNCoeLQ8LImdHp RGADet6kwDv64K5Lzcqsbp2JumsNvX9B/Ldxy9SEqBwFW/zbOvfKgObhnyKbrV3P hy/fue1FUkCoOUs7GoIK =cxHZ -----END PGP SIGNATURE----- --Sig_/+lykwUW3s=J_mz92qvd4V0v-- --===============0719400081== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0719400081==--