From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 10/25] drm/i915: Enable DP panel power
 sequencing for ValleyView
Date: Thu, 22 Mar 2012 11:31:05 -0700
Message-ID: <20120322113105.1e5c1e1a@bwidawsk.net>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Beeresh G <beeresh.g@intel.com>, intel-gfx@lists.freedesktop.org
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On Wed, 21 Mar 2012 12:48:31 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> VLV supports two dp panels, there are two set of panel power sequence
> registers which needed to be programmed based on the configured
> pipe. This patch add supports for the same
> 
> Signed-off-by: Beeresh G <beeresh.g@intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Ben Widawsky <ben@bwidawsk.net>