From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView Date: Thu, 22 Mar 2012 14:13:07 -0700 Message-ID: <20120322141307.3cd88f3f@jbarnes-desktop> References: <1332359326-15051-1-git-send-email-jbarnes@virtuousgeek.org> <1332359326-15051-20-git-send-email-jbarnes@virtuousgeek.org> <20120321213343.GK9913@phenom.ffwll.local> <20120321143647.2ecaeab9@jbarnes-desktop> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0369812733==" Return-path: Received: from oproxy7-pub.bluehost.com (oproxy7-pub.bluehost.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id 4F2299E763 for ; Thu, 22 Mar 2012 14:13:19 -0700 (PDT) In-Reply-To: <20120321143647.2ecaeab9@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0369812733== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/c9WxM=+dm3Jw4+P9cF2Gbld"; protocol="application/pgp-signature" --Sig_/c9WxM=+dm3Jw4+P9cF2Gbld Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Wed, 21 Mar 2012 14:36:47 -0700 Jesse Barnes wrote: > On Wed, 21 Mar 2012 22:33:43 +0100 > Daniel Vetter wrote: >=20 > > On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote: > > > Although internally the MMIO offsets for display regs haven't changed, > > > their visibility through the PCI BAR has been affected by the addition > > > of the Gunit, which occupies the low part of the address space. > > >=20 > > > Display regs on VLV are offset into the BAR by 0x180000, so we need to > > > add that for any display register offset. > > >=20 > > > This patch is a hack to do just that, but ultimately we need to split > > > our display and render code more cleanly and add accessor functions f= or > > > them. > > >=20 > > > Signed-off-by: Jesse Barnes > >=20 > > Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like > > you've proposed + I915_DISPLAY_READ/WRITE like we already have for the > > ring stuff is much better ... >=20 > I nearly got violent with the hw guys when they told me... >=20 > But yeah I think a display reg wrapper with an offset is probably the > least offensive. Ok started on this but quickly got frustrated. Should we apply this everywhere, even to PCH and ilk+ stuff? If not, it'll get inconsistent, if we do, it'll be confusing. I wonder if we should split intel_display.c first, and only apply the new macro to the gmch code? But that still leaves the various port files and gpio/gmbus... but those have pretty clear PCH splits too right? Suggestions welcome, but there may be no way to avoid a complete audit of every single read/write to see if it should be converted (ugg). --=20 Jesse Barnes, Intel Open Source Technology Center --Sig_/c9WxM=+dm3Jw4+P9cF2Gbld Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPa5XkAAoJEIEoDkX4Qk9h9RwQALedK5RfwL5OgIUhbhrc59+k 852BQHxLRZsOx1jhA0OGQDGkRbUtZa9vxPF014zUOzELnG2SI8oczqJ7tHiCQQl0 QkKi4zofG9EeczMxBapOdXIpipGmd4w6Ih2BNGDzc8KP0ZLBC+kRffHNILGp+Q8p 8C9/dQu15cOg//ZjNNFzeosUDvShdIVWdg56s65eqtTWzR9em9ARVBJmrOSkxAH4 KF+9dxAFRpJyG3AE29IMbpTjlfV4cCB8XIjchKaC9/+OKlBnbf0cWCXgGaKl8HiG 7RyfmuGRE/ThRT31kOIC3D/kiZdRU/a/Zoq0/1T72NAuxzZTMoYd6pD52cZqajam cG14+fmnLNAaCSIyqwi/4DXjf7jHm9dCKgwXvgbHaZ7UZY1y69rx1TVP01eDeAIn ilUl4VNVjgV6YF9ZIXm5Gtfwq9h8/K4bifgqC359SjH3vjTCwK0kWor8f188+dfw uy/MXm/+amLI7L3VRqA1rmc/zpi9F/KpSnjwITg1JZLx2boDpTJJETLcZ64UMvpg 142lSwfr+KJke/SL22TMJAS2X87CmJRBWv5f+tiJzXWy3g6TC0MUXFiCFXvvxrFK xQ9Po0NF+WJqhoETScSQVMJhvWeg3ZgyqoIlghvr0meIk636rR/ff9iWyadHNsqb t2FTK3pAsibA3he0vsyT =kcVa -----END PGP SIGNATURE----- --Sig_/c9WxM=+dm3Jw4+P9cF2Gbld-- --===============0369812733== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0369812733==--