From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 20/26] drm/i915: ValleyView has limited cacheability Date: Wed, 28 Mar 2012 10:43:02 -0700 Message-ID: <20120328104302.45203e6a@jbarnes-desktop> References: <1332452348-8814-1-git-send-email-jbarnes@virtuousgeek.org> <1332452348-8814-21-git-send-email-jbarnes@virtuousgeek.org> <20120326183420.GC17740@bolo_yeung.jf.intel.com> <20120326184945.GZ4014@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1453787227==" Return-path: Received: from oproxy8-pub.bluehost.com (oproxy8-pub.bluehost.com [69.89.22.20]) by gabe.freedesktop.org (Postfix) with SMTP id 1A69C9E744 for ; Wed, 28 Mar 2012 10:43:09 -0700 (PDT) In-Reply-To: <20120326184945.GZ4014@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Ben Widawsky , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1453787227== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/_HmR2+WSKoMXy7TpkUMamuu"; protocol="application/pgp-signature" --Sig_/_HmR2+WSKoMXy7TpkUMamuu Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 26 Mar 2012 20:49:45 +0200 Daniel Vetter wrote: > On Mon, Mar 26, 2012 at 11:34:21AM -0700, Ben Widawsky wrote: > > On Thu, Mar 22, 2012 at 02:39:02PM -0700, Jesse Barnes wrote: > > > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when > > > it does writes, so we can't use the cache bits the same way. > >=20 > > I found this commit message to be confusing. Is it simply saying CPU > > writes are snooped by the GT, but GT writes are not snooped bv the CPU? > >=20 > > >=20 > > > So map the status and pipe control pages as uncached on ValleyView, a= nd > > > only set the pages to cached if we're on a supported platform. > >=20 > > I'd like to see in the commit message why the pipe control page needs to > > be uncached. The only workarounds on the top of my head don't care about > > the coherency. >=20 > Afaik we've cleared this up in our mtg yesterday: > - Full coherent gtt mappings work, they simply moved the bit around (we > need to set bit2 instead of bit1 like on snb/ivb). > - It sounds like all the gpu functions can handle coherent memory, like > on snb/ivb. But because there's no shared cache between the gpu and the > cpu you don't gain anything, but only lose due to the required snoop > traffic. > - Because there's no last level cache it also means that when the gpu does > a write and snoops the cpu cache, it essentially means the cpu > completely drops it's cacheline and has to go back to main memory > (instead of l3 like it does on llc platforms). Gpu reads snoop the cpu > cache corectly. >=20 > I hope this clears up the confusion around coherency on vlv. Let Jesse > only needs to check with a real piece of silicon whether that's true ;-) > -Daniel Right, this patch is bogus; VLV should be just as capable here, so we can drop this one and I'll verify the cache bits. --=20 Jesse Barnes, Intel Open Source Technology Center --Sig_/_HmR2+WSKoMXy7TpkUMamuu Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPc02mAAoJEIEoDkX4Qk9hwZkQAKXg4puxQatDG1jbGkIE0IyT JP9qpOk8UGZ2oZyLlFVEXy/vuKLnT7PQpXb6wmc0toVVV2pCAvLsn9VkyBTEyvyV bzt4u8u0T2hFoUVjB09vF/5C3fRFv/bo2PJjo1b78Nt4yFAcZXDgz1oS5YHfGiSa WjCTI20CJc/2H0zpMvXC5bvOZklSW49ysB0wXYGmhJTknvC/n0h0JawnvSEX0YfH XukiPGJeuX/iS6IgexGzcJnyQn7QxDEGGSIW5GCDeMyV9rL3lvTqk/egfaTmWgOP Xs7xrAAiei9BDPdV/CzBKkjXWNQ35dPKLHuzkf424jWFMP7JWf5OZLsBoFM8LCTM +jxcyM4RFyW9xmkAvGdqmMywE3jzgi24GlSPTO1DtboffkgkGFsaIu4OD33HCZcl ZwqyGlQX5AvCqtM6aDNxgwb07qPn4gklKUuPa8WNAMbkCKIv6Tqqr3c7beJgFJaw Wgl7lh2VLFrApfAWgFm9tX/sEnnHiMvonGpHlDUm6vPXwJTA20hDqF20zrGSnHMU XOz8RplVwhlVq3e83IsjEOmiVRGkPqwoqH0o4anzevT5qDegeyw/VjhJfkfr7xGB ZK1yXXyC1dZVr3KdxmiTwQeQu5278AkfRgE37brLr/om6rd5qVehqRZxFxraAWuj rSMi+OzrZkJxyYvD0/V8 =ShQS -----END PGP SIGNATURE----- --Sig_/_HmR2+WSKoMXy7TpkUMamuu-- --===============1453787227== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1453787227==--