From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 1/2] drm/i915: ring irq cleanups
Date: Fri, 30 Mar 2012 17:18:23 +0200
Message-ID: <20120330151823.GA10925@phenom.ffwll.local>
References: <1333073487-4138-1-git-send-email-ben@bwidawsk.net>
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To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <ben@bwidawsk.net>, intel-gfx@lists.freedesktop.org, Ben Widawsky <benjamin.widawsky@intel.com>
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On Fri, Mar 30, 2012 at 09:33:22AM +0100, Chris Wilson wrote:
> On Thu, 29 Mar 2012 19:11:26 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> > - gen6 put/get only need one argument
> >     rflags and gflags are always the same (see above explanation)
> > - remove a couple redundantly defined IRQs
> > - reordered some lines to make things go in descending order
> > 
> > Every ring has its own interrupts, enables, masks, and status bits that
> > are fed into the main interrupt enable/mask/status registers. At one
> > point in time it seemed like a good idea to make our functions support
> > the notion that each interrupt may have a different bit position in the
> > corresponding register (blitter parser error may be bit n in IMR, but
> > bit m in blitter IMR). It turned out though that the HW designers did us
> > a solid on Gen6+ and this unfortunate situation has been avoided. This
> > allows our interrupt code to be cleaned up a bit.
> > 
> > I jammed this into one commit because there should be no functional
> > change with this commit, and staging it into multiple commits was
> > unnecessarily artificial IMO.
> > 
> > CC: Chris Wilson <chris@chris-wilson.co.uk>
> > CC: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> 
> Those two patches are
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Both patches applied, with a few things added to i915_reg.h for the first
one - I got confused about this stuff too much. Thanks for wrestling that
red dragon.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48