[PATCH] Mask reserved bits in display/sprite address registers

[PATCH] Mask reserved bits in display/sprite address registers

[Reese, Armin C]

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The patch file for this change is attached.  Had to send it from Outlook and wanted to avoid corrupting the patch. Hence, the attachment.

Armin

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From fed742d60b110b21495fd2214e61e252b32e8c68 Mon Sep 17 00:00:00 2001
From: acreese <armin.c.reese@intel.com>
Date: Fri, 30 Mar 2012 16:20:16 -0700
Subject: [PATCH] Mask reserved bits in display/sprite address registers

The purpose of this patch is to avoid zeroing the lower 12 reserved bits
of surface base address registers (framebuffer & sprite).  There are bits
in that range that may occasionally be set by BIOS or by other components.

Signed-off-by: acreese <armin.c.reese@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |    3 ++-
 drivers/gpu/drm/i915/i915_reg.h      |    9 +++++++++
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 drivers/gpu/drm/i915/intel_sprite.c  |    8 ++++----
 4 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 998116e..56551b4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1250,7 +1250,8 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 	obj = work->pending_flip_obj;
 	if (INTEL_INFO(dev)->gen >= 4) {
 		int dspsurf = DSPSURF(intel_crtc->plane);
-		stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
+		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
+					obj->gtt_offset;
 	} else {
 		int dspaddr = DSPADDR(intel_crtc->plane);
 		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..aea5667 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2724,6 +2724,15 @@
 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
 
+/* Display/Sprite base address macros */
+#define DISP_BASEADDR_MASK	(0xfffff000)
+#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
+#define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
+#define I915_MODIFY_DISPBASE(reg, gfx_addr) \
+				(I915_WRITE(reg, \
+					I915_LO_DISPBASE(I915_READ(reg)) | \
+					I915_HI_DISPBASE(gfx_addr)))
+
 /* VBIOS flags */
 #define SWF00			0x71410
 #define SWF01			0x71414
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a0e3166..fd7286c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2159,7 +2159,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 		      Start, Offset, x, y, fb->pitches[0]);
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
 	if (INTEL_INFO(dev)->gen >= 4) {
-		I915_WRITE(DSPSURF(plane), Start);
+		I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE(DSPADDR(plane), Offset);
 	} else
@@ -2239,7 +2239,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
 		      Start, Offset, x, y, fb->pitches[0]);
 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
-	I915_WRITE(DSPSURF(plane), Start);
+	I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
 	I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
 	I915_WRITE(DSPADDR(plane), Offset);
 	POSTING_READ(reg);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 98444ab..c88be5f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -134,7 +134,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 	I915_WRITE(SPRSCALE(pipe), sprscale);
 	I915_WRITE(SPRCTL(pipe), sprctl);
-	I915_WRITE(SPRSURF(pipe), obj->gtt_offset);
+	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);
 	POSTING_READ(SPRSURF(pipe));
 }
 
@@ -150,7 +150,7 @@ ivb_disable_plane(struct drm_plane *plane)
 	/* Can't leave the scaler enabled... */
 	I915_WRITE(SPRSCALE(pipe), 0);
 	/* Activate double buffered register update */
-	I915_WRITE(SPRSURF(pipe), 0);
+	I915_WRITE(SPRSURF(pipe), I915_LO_DISPBASE(I915_READ(SPRSURF(pipe))));
 	POSTING_READ(SPRSURF(pipe));
 }
 
@@ -291,7 +291,7 @@ snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 	I915_WRITE(DVSSCALE(pipe), dvsscale);
 	I915_WRITE(DVSCNTR(pipe), dvscntr);
-	I915_WRITE(DVSSURF(pipe), obj->gtt_offset);
+	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);
 	POSTING_READ(DVSSURF(pipe));
 }
 
@@ -307,7 +307,7 @@ snb_disable_plane(struct drm_plane *plane)
 	/* Disable the scaler */
 	I915_WRITE(DVSSCALE(pipe), 0);
 	/* Flush double buffered register updates */
-	I915_WRITE(DVSSURF(pipe), 0);
+	I915_WRITE(DVSSURF(pipe), I915_LO_DISPBASE(I915_READ(DVSSURF(pipe))));
 	POSTING_READ(DVSSURF(pipe));
 }
 
-- 
1.7.4.1


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Re: [PATCH] Mask reserved bits in display/sprite address registers

[Ben Widawsky]

On Thu, 5 Apr 2012 20:48:20 +0000
"Reese, Armin C" <armin.c.reese@intel.com> wrote:

> The patch file for this change is attached.  Had to send it from
> Outlook and wanted to avoid corrupting the patch. Hence, the
> attachment.
> 
> Armin

I don't know about the pipe stuff, but anything with gtt_offset should
always be PAGE_OFFSET, and so most of the macro stuff is way overkill
there. The only change is when you compare DISPSURF to gtt_offset, where
it would be easier to just use PAGE_MASK.

Ben

Re: [PATCH] Mask reserved bits in display/sprite address registers

[Reese, Armin C]

Thanks for the review, Ben.

Yes, I was a bit paranoid about what values could be in gtt_offset. But if it's always a multiple of 0x1000, we can save an additional mask operation.  I'll make the change and resubmit.

Armin

-----Original Message-----
From: Ben Widawsky [mailto:ben@bwidawsk.net] 
Sent: Friday, April 06, 2012 4:26 PM
To: Reese, Armin C
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] Mask reserved bits in display/sprite address registers

On Thu, 5 Apr 2012 20:48:20 +0000
"Reese, Armin C" <armin.c.reese@intel.com> wrote:

> The patch file for this change is attached.  Had to send it from 
> Outlook and wanted to avoid corrupting the patch. Hence, the 
> attachment.
> 
> Armin

I don't know about the pipe stuff, but anything with gtt_offset should always be PAGE_OFFSET, and so most of the macro stuff is way overkill there. The only change is when you compare DISPSURF to gtt_offset, where it would be easier to just use PAGE_MASK.


Ben

Re: [PATCH] Mask reserved bits in display/sprite address registers

[Daniel Vetter]

On Mon, Apr 09, 2012 at 03:48:03PM +0000, Reese, Armin C wrote:
> Thanks for the review, Ben.
> 
> Yes, I was a bit paranoid about what values could be in gtt_offset. But
> if it's always a multiple of 0x1000, we can save an additional mask
> operation.  I'll make the change and resubmit.

And a small style nitpick: Please prepend "drm/i915: " to your patch
headline when resending.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48