From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 1/4] drm/i915: handle input/output sdvo timings separately in mode_set Date: Tue, 10 Apr 2012 09:59:51 -0700 Message-ID: <20120410095951.6a5d058c@jbarnes-desktop> References: <1334058949-5633-1-git-send-email-daniel.vetter@ffwll.ch> <1334058949-5633-2-git-send-email-daniel.vetter@ffwll.ch> <20120410091737.4cfb056d@jbarnes-desktop> <20120410163649.GK4115@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0191612122==" Return-path: Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by gabe.freedesktop.org (Postfix) with SMTP id 31A829E93E for ; Tue, 10 Apr 2012 09:59:58 -0700 (PDT) In-Reply-To: <20120410163649.GK4115@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Daniel Vetter , Intel Graphics Development , DRI Development List-Id: intel-gfx@lists.freedesktop.org --===============0191612122== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/7SJdsXHXBUS7as+XNPBMQXv"; protocol="application/pgp-signature" --Sig_/7SJdsXHXBUS7as+XNPBMQXv Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Tue, 10 Apr 2012 18:36:49 +0200 Daniel Vetter wrote: > Well, neither do I have a clue about sdvo, but I think I somewhat > self-consistent explanation for what's going on. >=20 > Sdvo seems to have two timings, one is the output timing which will be > sent over whatever is connected on the other side of the sdvo chip (panel, > hdmi screen, tv), the other is the input timing which will be generated by > the gmch pipe. It looks like sdvo is expected to scale between the two. Correct. And the SDVO encoder in the display engine will always run the clock at 100MHz+ and do data stuffing if the pixel rate is lower than that, but we need to set the right clock multiplier in that case (which we do). > To make things slightly more complicated, we have a bunch of special > cases: > - for lvds panel we always use a fixed output timing, namely > intel_sdvo->sdvo_lvds_fixed_mode, hence that special case. > - sdvo has an interface to generate a preferred input timing for a given > output timing. This is the confusing thing that I've tried to clear up > with the follow-on patches. > - a special requirement is that the input pixel clock needs to be between > 100MHz and 200MHz (likely to keep it within the electromechanical design > range of PCIe). Lower pixel clocks are doubled/quadrupled. >=20 > The thing this patch tries to fix is that the pipe needs to be explicit > instructed to double/quadruple the pixels and needs the correspondingly > higher pixel clock, whereas the sdvo adaptor seems to do that itself and > needs the unadjusted pixel clock. Yeah that sounds right based on my reading of an old spec I have. > This patch tries to fix this mess by > - keeping the output mode timing in the unadjusted plain mode, safe for > the lvds case. > - store the input timing in the adjusted_mode with the adjusted pixel > clock. This way we don't need to frob around with the core crtc mode set > code. > - fixup the pixelclock when constructing the sdvo dtd timing struct. This > is why the first part of the patch is an integral part of the series. > - the is_tv special case can be dropped because input_dtd is equivalent to > adjusted_mode after these changes. Follow-up patches clear this up > further (by simply ripping out intel_sdvo->input_dtd because it's not > needed). >=20 > Hopefully this clears things up a bit. Yep, thanks. Hopefully you'll get your SDVO spec access soon... --=20 Jesse Barnes, Intel Open Source Technology Center --Sig_/7SJdsXHXBUS7as+XNPBMQXv Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJPhGcHAAoJEIEoDkX4Qk9hrZQP/RkGpYfcxojYHxxMV5mGYQ32 ymu4jd/cR56Qv84G6TbDGNbgR63cmZgQWc6QX0Lfe78cARiX6Qq2nSCX3p4yDeGo zYBo4r5Nd+Ms3IgZAuPOsCJ3qnnaAkfaRyhkBQZlBdOzCM9NK11CsaL7WJifwfrp nEqcxHMLjkitgNgquPrxJw0+fD8T6Ah5Q8gUqQP2fcpTEseHvyrSX2Bjd8MlTf/y bQyg//FOPlj5EpCpBAOiYA3JjuX9uUIMvvgDKzf4Ili+sc6tug7bbaVPMfLgq3Rv HKtt+rab4Uq7iB8fhC+9+wGUxK3GtlyLnSitfnPMgR5X0x/UkRJrb6u6qGZN8jTw TNQEopSTuWH9tC9VzYjhZpxpWfr6PZ7gXm3eAparZaEs9nmKFOdgFfO/hNmSB4fr f57W4bB5/r3s4cCboVe+rcAcQUrQqJxHp/kN3M6szhOkqDYHxjDyZ5XTXzUQrvQy w2xWiMoYIg8psG4bIhSuSmGLDHIZqdJJlxJCDSqs57tjvrlwHlcDkXItg+t3zyR4 IAnzwHGZe8GXqkCHpiZIeI5XVUpAfdhW0co0xA8blaiLqGh8S1dKzd76FxaLCi3q 84uJznO5WUzYfYtBTTo0rZl38iyb49nmAzjV1FPssqIawZSszb0BJoOpY+HixA9M MFMl9Y491cfTg2+J1lZO =A25v -----END PGP SIGNATURE----- --Sig_/7SJdsXHXBUS7as+XNPBMQXv-- --===============0191612122== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0191612122==--