From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 11/29] drm/i915: share pipe count handling
 with Ivybridge
Date: Tue, 17 Apr 2012 12:19:16 +0200
Message-ID: <20120417101916.GF4104@phenom.ffwll.local>
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To: Eugeni Dodonov <eugeni.dodonov@intel.com>
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On Fri, Apr 13, 2012 at 05:08:47PM -0300, Eugeni Dodonov wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3d78686..5ee652d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2427,7 +2427,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
>  	case 1:
>  		break;
>  	case 2:
> -		if (IS_IVYBRIDGE(dev))
> +		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>  			break;
>  		/* fall through otherwise */
>  	default:

Imo this code is a rather funky way to check for 3 plane support ... I
think we should just replace this entire switch statement with a
if(WARN_ON(intel_crtc->plane > dev_priv->num_pipes)) return -EINVAL;

Or has there been another reason for this? Chris, git blame says you've
originally added this in 5c3b82e2, any comments?
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48