From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Mask reserved bits in display/sprite address registers Date: Tue, 17 Apr 2012 17:55:32 +0200 Message-ID: <20120417155532.GP4104@phenom.ffwll.local> References: <07EEC142D30DAC40BA4DD9C0F9EE51090E40E8@FMSMSX102.amr.corp.intel.com> <07EEC142D30DAC40BA4DD9C0F9EE51090E5110@FMSMSX102.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 772179F311 for ; Tue, 17 Apr 2012 08:54:36 -0700 (PDT) Received: by werp11 with SMTP id p11so4998616wer.36 for ; Tue, 17 Apr 2012 08:54:35 -0700 (PDT) Content-Disposition: inline In-Reply-To: <07EEC142D30DAC40BA4DD9C0F9EE51090E5110@FMSMSX102.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: "Reese, Armin C" Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 16, 2012 at 09:02:41PM +0000, Reese, Armin C wrote: > Corrected my name in the patch (acreese -> Armin Reese) ... > > The attached patch file was updated to reflect reviewer's comments. The > only change I did not make was using PAGE_MASK instead of > DISP_BASEADDR_MASK. PAGE_MASK is CPU architecture dependent and I > didn't want to tie our GPU addressing arch to that of the CPU. Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48