From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: manage PCH PLLs separately from pipes Date: Wed, 18 Apr 2012 09:55:37 -0700 Message-ID: <20120418095537.7d70d703@jbarnes-desktop> References: <1334179003-1592-1-git-send-email-jbarnes@virtuousgeek.org> <1334337878-32566-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by gabe.freedesktop.org (Postfix) with SMTP id 8DE4A9E7E1 for ; Wed, 18 Apr 2012 09:55:40 -0700 (PDT) In-Reply-To: <1334337878-32566-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 13 Apr 2012 18:24:38 +0100 Chris Wilson wrote: > From: Jesse Barnes > > PCH PLLs aren't required for outputs on the CPU, so we shouldn't just > treat them as part of the pipe. > > So split the code out and manage PCH PLLs separately, allocating them > when needed or trying to re-use existing PCH PLL setups when the timings > match. > > v2: add num_pch_pll field to dev_priv (Daniel) > don't NULL the pch_pll pointer in disable or DPMS will fail (Jesse) > put register offsets in pll struct (Chris) > > v3: Decouple enable/disable of PLLs from get/put. > > Fixes https://bugs.freedesktop.org/show_bug.cgi?id=44309 > > Signed-off-by: Jesse Barnes > Signed-off-by: Chris Wilson > --- I think this one can be applied. I still have a mode setting issue, but this patch at least lets me see the error rather than hiding it behind an -EINVAL. Any my issue could be due to some early hardware anyway; I'll verify once I get my upgrade. Thanks, -- Jesse Barnes, Intel Open Source Technology Center