From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [RFC] drm/i915: check FDI config for 3 pipe
Date: Wed, 18 Apr 2012 15:32:10 -0700
Message-ID: <20120418153210.0f428236@jbarnes-desktop>
References: <20120418142536.1457193c@jbarnes-desktop>
	<20120418152744.649c2970@jbarnes-desktop>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from oproxy8-pub.bluehost.com (oproxy8-pub.bluehost.com
	[69.89.22.20])
	by gabe.freedesktop.org (Postfix) with SMTP id 7CCA89E753
	for <intel-gfx@lists.freedesktop.org>;
	Wed, 18 Apr 2012 15:32:13 -0700 (PDT)
Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189]
	helo=jbarnes-desktop)
	by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128)
	(Exim 4.76) (envelope-from <jbarnes@virtuousgeek.org>)
	id 1SKdQ4-0001Wj-LJ
	for intel-gfx@lists.freedesktop.org; Wed, 18 Apr 2012 16:32:12 -0600
In-Reply-To: <20120418152744.649c2970@jbarnes-desktop>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Wed, 18 Apr 2012 15:27:44 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> On Wed, 18 Apr 2012 14:25:36 -0700
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > Three pipe can only be enabled in some cases and updated docs indicate
> > a bit to control FDI B+C sharing.
> > 
> > This patch adds a check to make sure we can support a given config with
> > the existing FDI lane configuration, and tries to set the bit as
> > appropriate.
> > 
> > We may want to go further though and just totally break the link
> > between our pipes, planes, PLLs, FDI lanes, transcoders, etc and the
> > CRTCs we expose to userspace.  We could theoretically just allocate new
> > ones every mode set.  That wouldn't help a whole lot though since we
> > don't get full configuration changes from userspace, just a small
> > window of CRTC data with no idea of what might happen next...
> 
> Ah just found a bug in reviewing my own patch here.
> 
> +	if (intel_crtc->pipe > 1) {
> +		if (intel_crtc->fdi_lanes > 2)
> +			I915_WRITE(SOUTH_CHICKEN1, I915_READ(SOUTH_CHICKEN1) &
> +				   ~FDIBC_LANE_SHARE_EN);
> +		else
> +			I915_WRITE(SOUTH_CHICKEN1, I915_READ(SOUTH_CHICKEN1) |
> +				   FDIBC_LANE_SHARE_EN);
> +	}
> 
> Should be if (intel_crtc->pipe > 0) since we need to apply this when
> either FDI C *or* B changes config.
> 
> I'll try, maybe it'll help with the funky 3 pipe config mode set
> problem I saw.

Oh and this hunk belongs in the IVB function!

-- 
Jesse Barnes, Intel Open Source Technology Center