From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915: rc6 residency (fix the fix)
Date: Sun, 22 Apr 2012 10:35:29 -0700
Message-ID: <20120422103529.54504e03@bwidawsk.net>
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To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, Ben Widawsky <benjamin.widawsky@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Sun, 22 Apr 2012 16:49:53 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Fri, 20 Apr 2012 11:50:01 -0700, Ben Widawsky <ben@bwidawsk.net>
> wrote:
> > Chris' fix for my 32b breakage was incorrect. do_div returns a
> > remainder. Go back to a divide macro which is more 32b friendly.
> > 
> > Tested on x86-64.
> > 
> > This has only been compile tested on 32b systems.
> Doesn't compile on my 32-bit systems.
> 
> Still does a 64-bit divide.

This is weird. I don't understand what's broken exactly. It should be
dividing an unsigned long long, which the 32b compiler should have no
issue with. The macro itself expands to do_div which was your original
fix.

What is the error message you get?

>  
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48756
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_sysfs.c |    4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
> > b/drivers/gpu/drm/i915/i915_sysfs.c index f1b5108..bd6350b 100644
> > --- a/drivers/gpu/drm/i915/i915_sysfs.c
> > +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> > @@ -39,8 +39,8 @@ static u32 calc_residency(struct drm_device *dev,
> > const u32 reg) if (!intel_enable_rc6(dev))
> >  		return 0;
> >  
> > -	raw_time = I915_READ(reg) * 128ULL + 500;
> > -	return do_div(raw_time, 100000);
> > +	raw_time = I915_READ(reg) * 128ULL;
> > +	return DIV_ROUND_UP_ULL(raw_time, 1000) / 100;
> return (u32)DIV_ROUND_UP_ULL(raw_time, 1000) / 100;
> -Chris
>