Re: [PATCH 2/5] drm/i915: Dynamic Parity Detection handling

Jesse Barnes
2012-05-25T18:06:21Z

On Fri, 25 May 2012 10:34:58 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > + misccpctl = I915_READ(GEN7_MISCCPCTL);
> > + I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>
> DOP clock gating should be unconditionally disabled, you can move this
> to the clock gating routine.

Ok I dug into this at your prodding and take it back. We can leave DOP
clock gating enabled; only VLV needs the unconditional disable, so we
don't need to worry about this if/until we add DPF there.

--
Jesse Barnes, Intel Open Source Technology Center