From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Do not read non-existent DPLL registers on PCH hardware Date: Wed, 2 May 2012 14:35:34 +0200 Message-ID: <20120502123534.GC5089@phenom.ffwll.local> References: <1335956826-22460-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ey0-f177.google.com (mail-ey0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id AC69A9E73F for ; Wed, 2 May 2012 05:34:29 -0700 (PDT) Received: by eaak13 with SMTP id k13so156471eaa.36 for ; Wed, 02 May 2012 05:34:28 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1335956826-22460-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, May 02, 2012 at 12:07:06PM +0100, Chris Wilson wrote: > We only execute intel_decrease_pllclock for pre-PCH hardware, typically > gen4 mobiles. However, in the variable declaration we did read from the > non-PCH DPLL register, quite naughty and detected by SandyBridge. > > Reported-by: Andrey Rahmatullin > References: https://bugs.freedesktop.org/show_bug.cgi?id=49025 > Signed-off-by: Chris Wilson Picked up for -fixes (with Andrey's tested-by added), thanks for the patch. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48