From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 02/14] drm/i915: DSL_LINEMASK is 12 bits
 only on gen2
Date: Tue, 8 May 2012 14:27:29 +0200
Message-ID: <20120508122729.GH4802@phenom.ffwll.local>
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To: Paulo Zanoni <przanoni@gmail.com>
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On Tue, May 08, 2012 at 01:49:36PM +0200, Daniel Vetter wrote:
> On Fri, May 04, 2012 at 05:18:14PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > 
> > Gen3+ is 13 bits (12:0), and on gen2 only 12 (11:0). For both the high
> > bits are marked reserved, read-only so continue to mask them. Bit 31
> > is not reserved and has a meaning.
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Queued for -next, thanks for the patch. While reading through the code
> I've noticed that there are other places where we get this wrong. In the
> crt load detect code we don't even bother with properly masking, and in
> the precise vblank timestamp code we always use the gen3+ mask. That code
> in addition doesn't properly handle the lack of the PIPEDSL register on
> ilk+. Can I volunteer you to look into that?

Scrap the last remark, if mixed up PIPEDSL with PIPESTAT.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48