From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: gen6_enable_rps() wants to be called after ring initialisation Date: Wed, 9 May 2012 21:59:48 +0200 Message-ID: <20120509195948.GC4963@phenom.ffwll.local> References: <20120502204159.GA4101@phenom.ffwll.local> <1336560988-1716-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id BC5919F399 for ; Wed, 9 May 2012 12:58:39 -0700 (PDT) Received: by werp11 with SMTP id p11so585139wer.36 for ; Wed, 09 May 2012 12:58:38 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1336560988-1716-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, May 09, 2012 at 11:56:28AM +0100, Chris Wilson wrote: > Currently we call gen6_enable_rps() (which writes into the per-ring > register mmio space) from intel_modeset_init_hw() which is called before > we initialise the rings. If we defer intel_modeset_init_hw() until > afterwards (in the intel_modeset_gem_init() phase) all is well. > > v2: Rectify ordering of gem vs display HW init upon resume. (Daniel) > > Signed-off-by: Chris Wilson Queued for -next, thanks for the patch. We still have a few strange things in our hw setup paths, but that can be cleanup up later on. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48