From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 2/2] drm/i915: Enable the PCH PLL for all generations after link training Date: Mon, 14 May 2012 08:12:13 -0700 Message-ID: <20120514081213.76b208cb@jbarnes-desktop> References: <1336899249-2612-1-git-send-email-chris@chris-wilson.co.uk> <1336899249-2612-2-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id AC76F9F660 for ; Mon, 14 May 2012 08:12:18 -0700 (PDT) In-Reply-To: <1336899249-2612-2-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sun, 13 May 2012 09:54:09 +0100 Chris Wilson wrote: > Hidden away within one chipset specific path was the necessary logic to > turn on the PLL. This needs to be done everywhere in order for us to > drive any display! As such as soon as we tested on a non-CougarPoint > chipset, we failed to bring up any DisplayPorts and generated a nice set > of assertion failures in the process. At least one part of our logic is > working, the part that assumes that we have no idea what we are doing. > > Reported-by: guang.a.yang@intel.com > References: https://bugs.freedesktop.org/show_bug.cgi?id=49712 > Signed-off-by: Chris Wilson > Cc: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a679a9a..d0112ec 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2887,14 +2887,14 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > /* For PCH output, training FDI link */ > dev_priv->display.fdi_link_train(crtc); > > + intel_enable_pch_pll(intel_crtc); > + > if (HAS_PCH_LPT(dev)) { > DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); > lpt_program_iclkip(crtc); > } else if (HAS_PCH_CPT(dev)) { > u32 sel; > > - intel_enable_pch_pll(intel_crtc); > - > temp = I915_READ(PCH_DPLL_SEL); > switch (pipe) { > default: Thanks Chris. Only thing I'm not sure about is the LPT bit; does this function do what we want there? Other than that: Reviewed-by: Jesse Barnes Thanks, -- Jesse Barnes, Intel Open Source Technology Center