From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView Date: Wed, 20 Jun 2012 08:35:08 -0700 Message-ID: <20120620083508.4f3e150b@jbarnes-desktop> References: <1339786526-16747-1-git-send-email-jbarnes@virtuousgeek.org> <1339786526-16747-7-git-send-email-jbarnes@virtuousgeek.org> <20120620125717.GG7170@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy7-pub.bluehost.com (oproxy7-pub.bluehost.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id 71C4DA030B for ; Wed, 20 Jun 2012 08:41:38 -0700 (PDT) In-Reply-To: <20120620125717.GG7170@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 20 Jun 2012 14:57:17 +0200 Daniel Vetter wrote: > On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote: > > The PTE format is similar to SNB, but we don't support an MLC and don't > > need chipset flushing. > > > > Signed-off-by: Jesse Barnes > > I have my questions whether this is right, given that MLC died for snb & > ivb, that ivb has grown a L3$ cache instead (which vlv seems to have, too) > and that the LLC bit here isn't actually LLC, but just means 'snoop cpu > caches'. Yeah I dropped the MLC part and didn't rename the LLC bit which might be a little confusing, but afaict from the VLV docs this is correct and actually works here (i.e. my last "cacheability is different" patch is unneeded). -- Jesse Barnes, Intel Open Source Technology Center