From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView Date: Wed, 20 Jun 2012 14:57:17 +0200 Message-ID: <20120620125717.GG7170@phenom.ffwll.local> References: <1339786526-16747-1-git-send-email-jbarnes@virtuousgeek.org> <1339786526-16747-7-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id E0753A0A54 for ; Wed, 20 Jun 2012 05:55:43 -0700 (PDT) Received: by bkwj4 with SMTP id j4so6932044bkw.36 for ; Wed, 20 Jun 2012 05:55:43 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1339786526-16747-7-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Jun 15, 2012 at 11:55:19AM -0700, Jesse Barnes wrote: > The PTE format is similar to SNB, but we don't support an MLC and don't > need chipset flushing. > > Signed-off-by: Jesse Barnes I have my questions whether this is right, given that MLC died for snb & ivb, that ivb has grown a L3$ cache instead (which vlv seems to have, too) and that the LLC bit here isn't actually LLC, but just means 'snoop cpu caches'. But I plan to burn this all with the heat of a thousands suns in my gtt rework, so who cares ;-) -Daniel > --- > drivers/char/agp/intel-gtt.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c > index 1237e75..c1e2943 100644 > --- a/drivers/char/agp/intel-gtt.c > +++ b/drivers/char/agp/intel-gtt.c > @@ -1182,9 +1182,17 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, > static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, > unsigned int flags) > { > + unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; > + unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; > u32 pte_flags; > > - pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; > + if (type_mask == AGP_USER_MEMORY) > + pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; > + else { > + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; > + if (gfdt) > + pte_flags |= GEN6_PTE_GFDT; > + } > > /* gen6 has bit11-4 for physical addr bit39-32 */ > addr |= (addr >> 28) & 0xff0; > @@ -1379,7 +1387,6 @@ static const struct intel_gtt_driver valleyview_gtt_driver = { > .write_entry = valleyview_write_entry, > .dma_mask_size = 40, > .check_flags = gen6_check_flags, > - .chipset_flush = i9xx_chipset_flush, > }; > > /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48