Re: [PATCH 21/21] drm/i915: enable RC6 workaround on Haswell

Daniel Vetter
2012-06-28T19:23:57Z

On Thu, Jun 28, 2012 at 03:55:49PM -0300, Eugeni Dodonov wrote:
> For Haswell, on some of the early hardware revisions, it is possible to
> run into issues when RC6 state is enabled and when pipes change state.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Given that this is a w/a that only applies for early silicon, please add a
comment that this should get nuked once production stuff ships.
-Daniel

> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 78b6ba4..fd55e91 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4512,4 +4512,9 @@
> #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
> #define SFUSE_STRAP_DDID_DETECTED (1<<0)
>
> +#define WM_DBG 0x45280
> +#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
> +#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
> +#define WM_DBG_DISALLOW_SPRITE (1<<2)
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0ccdb96..cc8628c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3601,6 +3601,15 @@ static void haswell_init_clock_gating(struct drm_device *dev)
> /* WaDisable4x2SubspanOptimization */
> I915_WRITE(CACHE_MODE_1,
> _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> +
> + /* Work-around rc6 issue */
> + I915_WRITE(WM_DBG,
> + I915_READ(WM_DBG) |
> + WM_DBG_DISALLOW_MULTIPLE_LP |
> + WM_DBG_DISALLOW_SPRITE |
> + WM_DBG_DISALLOW_MAXFIFO
> + );
> +
> }
>
> static void ivybridge_init_clock_gating(struct drm_device *dev)
> --
> 1.7.11.1
>
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--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48