From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 03/10] drm/i915: support Haswell force waking Date: Mon, 2 Jul 2012 09:49:38 -0700 Message-ID: <20120702094938.2acf6dd0@bwidawsk.net> References: <1341240671-5843-1-git-send-email-eugeni.dodonov@intel.com> <1341240671-5843-4-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 6778D9E78F for ; Mon, 2 Jul 2012 09:49:45 -0700 (PDT) In-Reply-To: <1341240671-5843-4-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eugeni Dodonov Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 2 Jul 2012 11:51:04 -0300 Eugeni Dodonov wrote: > There is a different ACK register for force wake on Haswell, so account > for that. Well I guess that HSW bit in patch 2 that I just acked didn't belong there yet ;-) Also, since you've now put conditional registers in get/put, why not go a step further and combine mt, and non-mt? > > Signed-off-by: Eugeni Dodonov Reviewed-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.c | 22 ++++++++++++++++++---- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 19 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index a4ea4a9..3ac414f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -451,12 +451,19 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > > static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > { > - if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0, 500)) > + u32 forcewake_ack; > + > + if (IS_HASWELL(dev_priv->dev)) > + forcewake_ack = FORCEWAKE_ACK_HSW; > + else > + forcewake_ack = FORCEWAKE_ACK; > + > + if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500)) > DRM_ERROR("Force wake wait timed out\n"); > > I915_WRITE_NOTRACE(FORCEWAKE, 1); > > - if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1), 500)) > + if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) > DRM_ERROR("Force wake wait timed out\n"); > > __gen6_gt_wait_for_thread_c0(dev_priv); > @@ -464,12 +471,19 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > > static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) > { > - if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0, 500)) > + u32 forcewake_ack; > + > + if (IS_HASWELL(dev_priv->dev)) > + forcewake_ack = FORCEWAKE_ACK_HSW; > + else > + forcewake_ack = FORCEWAKE_MT_ACK; > + > + if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500)) > DRM_ERROR("Force wake wait timed out\n"); > > I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); > > - if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1), 500)) > + if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) > DRM_ERROR("Force wake wait timed out\n"); > > __gen6_gt_wait_for_thread_c0(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 20f7f0d..f17de3d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4095,6 +4095,7 @@ > #define FORCEWAKE 0xA18C > #define FORCEWAKE_VLV 0x1300b0 > #define FORCEWAKE_ACK_VLV 0x1300b4 > +#define FORCEWAKE_ACK_HSW 0x130044 > #define FORCEWAKE_ACK 0x130090 > #define FORCEWAKE_MT 0xa188 /* multi-threaded */ > #define FORCEWAKE_MT_ACK 0x130040 -- Ben Widawsky, Intel Open Source Technology Center