From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 07/10] drm/i915: disable RC6 when disabling
 rps
Date: Mon, 2 Jul 2012 11:36:54 -0700
Message-ID: <20120702113654.047928ee@bwidawsk.net>
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To: Eugeni Dodonov <eugeni.dodonov@intel.com>
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On Mon,  2 Jul 2012 11:51:08 -0300
Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:

> We weren't disabling RC6 bits when bringing down RPS.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b00df1f..5ea8319 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2303,6 +2303,7 @@ static void gen6_disable_rps(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> +	I915_WRITE(GEN6_RC_CONTROL, 0);
>  	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
>  	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
>  	I915_WRITE(GEN6_PMIER, 0);

I think we really only need to clear bit 31 to disable (and enable
already sets it to 0) but this should be fine.

-- 
Ben Widawsky, Intel Open Source Technology Center