From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915: add register read IOCTL
Date: Thu, 12 Jul 2012 13:08:56 -0700
Message-ID: <20120712130856.64973401@bwidawsk.net>
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To: Eric Anholt <eric@anholt.net>
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On Thu, 12 Jul 2012 12:42:30 -0700
Eric Anholt <eric@anholt.net> wrote:

> Ben Widawsky <ben@bwidawsk.net> writes:
> 
> > The interface's immediate purpose is to do synchronous timestamp queries
> > as required by GL_TIMESTAMP. The GPU has a register for reading the
> > timestamp but because that would normally require root access, the
> > IOCTL can provide this service.
> >
> > Currently the implementation whitelists only the render ring timestamp
> > register, because that is the only thing we need to expose at this time.
> 
> Thanks. I was just writing this patch yesterday since it still hadn't
> landed.  What I was doing was very similar, I was just not including a
> size, since we're going to whitelist regs and the correct size is
> implied by the register offset.

Please check out:
1342116066-12164-1-git-send-email-ben@bwidawsk.net

We went through this all on IRC already ;-)

> 
> > +int i915_reg_read_ioctl(struct drm_device *dev,
> > +			void *data, struct drm_file *file)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct drm_i915_reg_read *reg = data;
> > +
> > +	/* Whitelisted for now */
> > +	if (reg->offset != RING_TIMESTAMP(RENDER_RING_BASE))
> > +		return -ENXIO;
> 
> Should this be conditional on the gen having the timestamp register?
> 
> > +struct drm_i915_reg_read {
> > +	__u64 offset;
> > +	__u32 size;
> > +	__u64 val; /* Return value */
> > +	__u32 pad;
> > +};
> 
> Bad padding here.  On i386 you'll get a struct like:
> 
> {
>         uint64_t offset
>         uint32_t size
>         uint32_t implicit_pad
>         uint64_t val
>         uint32_t pad
> }



-- 
Ben Widawsky, Intel Open Source Technology Center