From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Ajdust down threshold in intel_pm. Date: Mon, 16 Jul 2012 21:50:39 +0200 Message-ID: <20120716195039.GD5023@phenom.ffwll.local> References: <1341350202-8664-1-git-send-email-marcheu@chromium.org> <20120704075211.GF5375@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C2E99EE99 for ; Mon, 16 Jul 2012 12:50:35 -0700 (PDT) Received: by weyr3 with SMTP id r3so4478661wey.36 for ; Mon, 16 Jul 2012 12:50:34 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20120704075211.GF5375@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: =?iso-8859-1?Q?St=E9phane?= Marchesin Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jul 04, 2012 at 09:52:11AM +0200, Daniel Vetter wrote: > On Tue, Jul 03, 2012 at 02:16:42PM -0700, St=E9phane Marchesin wrote: > > The up and down thresholds are very asymetric, so it is possible > > to have a case where a spike of rendering increases the GPU clock to > > the max (because the up threshold is low) and then a simple blinking > > cursor is enough to keep the clock at the maximum speed forever > > (because the down threshold is high). > > = > > Lowering the down threshold allows the GPU clock to go back down even > > when there is a blinking cursor on the screen. > > = > > Signed-off-by: St=E9phane Marchesin > = > I've just merged Eugeni's hsw rc6 patches - those contain newly tuning > variables. Can you maybe try out whether these would have the same effect? > I'd prefer to simple enable these, presuming that the hw guys we've got > them from did some decent tuning ... Ping. 3.6 merge window is approach fast and I think I'd be good to get this in ... Or something similar, based on the hsw ratio between downclock and upclock limit, but with the slightly bigger thresholds used by ivb/snb for upclocks maybe? -Daniel -- = Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48