From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH intel-gpu-tools] tools: Added intel_dpio_read and intel_dpio_write Date: Mon, 6 Aug 2012 09:16:52 +0200 Message-ID: <20120806071652.GE5502@phenom.ffwll.local> References: <1343909236-17870-1-git-send-email-vijay.a.purushothaman@intel.com> <25e00d42d0c3a1f04db332d79a69b63d@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f41.google.com (mail-wg0-f41.google.com [74.125.82.41]) by gabe.freedesktop.org (Postfix) with ESMTP id CD2189E824 for ; Mon, 6 Aug 2012 00:16:33 -0700 (PDT) Received: by wgbds1 with SMTP id ds1so1145149wgb.0 for ; Mon, 06 Aug 2012 00:16:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <25e00d42d0c3a1f04db332d79a69b63d@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Aug 02, 2012 at 09:06:48AM -0700, Ben Widawsky wrote: > On 2012-08-02 05:07, Vijay Purushothaman wrote: > >In Valleyview the DPLL and lane control registers are accessible only > >through side band fabric called DPIO. Added two tools to read and > >write > >registers residing in this space. > > Could I convince you to use the centralized read/write mmio functions? > Otherwise, everything seems fine to me here. I wonder whether we need some kernel interface for this, after all if the kernel touches this, too, things will blow up. Otoh the kernel only uses the dpio sideband regs at modeset time, so I guess the risk is minimal. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48