From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6 Date: Wed, 8 Aug 2012 09:35:40 +0200 Message-ID: <20120808073540.GC5490@phenom.ffwll.local> References: <1342803748-25695-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B30C9E7A6 for ; Wed, 8 Aug 2012 00:35:21 -0700 (PDT) Received: by wgbdr1 with SMTP id dr1so329155wgb.12 for ; Wed, 08 Aug 2012 00:35:20 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1342803748-25695-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 20, 2012 at 06:02:28PM +0100, Chris Wilson wrote: > The requirements for the sync flush to be emitted prior to the render > cache flush is only true for SandyBridge. On IvyBridge and friends we > can just emit the flushes with an inline CS stall. > > Signed-off-by: Chris Wilson Since I've seen Ken ditch these w/a for ivb+ in mesa, I've figured that this is ok. Some bspec reading seems to agree. Merged to dinq, thanks for the patch. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48