From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 3/4] drm/i915: add workaround to gen7_render_ring_flush Date: Tue, 28 Aug 2012 11:17:26 +0200 Message-ID: <20120828091726.GB5125@phenom.ffwll.local> References: <1345239344-9968-1-git-send-email-przanoni@gmail.com> <1345239344-9968-4-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BD579F50C for ; Tue, 28 Aug 2012 02:17:01 -0700 (PDT) Received: by bkcji2 with SMTP id ji2so1616710bkc.36 for ; Tue, 28 Aug 2012 02:17:00 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1345239344-9968-4-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 17, 2012 at 06:35:43PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > The combination of this commit + the next one will prevent a lot of > gpu hangs. > > Signed-off-by: Paulo Zanoni tbh I'm not happy with the justification in the commit message here. If there's anything about this in Bspec, I want a full reference, if this is just due to the simulator, please say so (and maybe paste the complaint fulsim raises). If it's just empirical evidence please say which machines this affects (since afaict it's only confirmed to help on hsw). [Also directed at Ben.] Thanks, Daniel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index dc5272b..9895a6e 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -263,6 +263,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, > } > > static int > +gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) > +{ > + int ret; > + > + ret = intel_ring_begin(ring, 4); > + if (ret) > + return ret; > + > + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); > + intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | > + PIPE_CONTROL_STALL_AT_SCOREBOARD); > + intel_ring_emit(ring, 0); > + intel_ring_emit(ring, 0); > + intel_ring_advance(ring); > + > + return 0; > +} > + > +static int > gen7_render_ring_flush(struct intel_ring_buffer *ring, > u32 invalidate_domains, u32 flush_domains) > { > @@ -295,6 +314,11 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, > * TLB invalidate requires a post-sync write. > */ > flags |= PIPE_CONTROL_QW_WRITE; > + > + /* Workaround: we must issue a pipe_control with CS-stall bit > + * set before a pipe_control command that has the state cache > + * invalidate bit set. */ > + gen7_render_ring_cs_stall_wa(ring); > } > > ret = intel_ring_begin(ring, 4); > -- > 1.7.11.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48