From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB Date: Tue, 2 Oct 2012 16:51:39 -0700 Message-ID: <20121002165139.6e106276@bwidawsk.net> References: <1349217826-2538-1-git-send-email-jbarnes@virtuousgeek.org> <1349217826-2538-9-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from shiva.chad-versace.us (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 685859E7B5 for ; Tue, 2 Oct 2012 16:51:54 -0700 (PDT) In-Reply-To: <1349217826-2538-9-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 2 Oct 2012 17:43:42 -0500 Jesse Barnes wrote: > Workaround for dual port PS dispatch on GT1. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 400dd05..ce8d7b2 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3541,6 +3541,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > + /* WaDisablePSDDualDispatchEnable */ > + if (IS_MOBILE(dev)) > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + else > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); Seems like we need this on VLV too. Also, I can't find this register in the bspec, which is annoying - but I see the w/a. -- Ben Widawsky, Intel Open Source Technology Center