From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB Date: Wed, 3 Oct 2012 09:23:09 +0200 Message-ID: <20121003072309.GC5329@phenom.ffwll.local> References: <1349217826-2538-1-git-send-email-jbarnes@virtuousgeek.org> <1349217826-2538-8-git-send-email-jbarnes@virtuousgeek.org> <20121002164432.77bc2e8a@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 0ADD79E82D for ; Wed, 3 Oct 2012 00:22:16 -0700 (PDT) Received: by mail-wi0-f171.google.com with SMTP id hj13so1635249wib.12 for ; Wed, 03 Oct 2012 00:22:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20121002164432.77bc2e8a@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Oct 02, 2012 at 04:44:32PM -0700, Ben Widawsky wrote: > On Tue, 2 Oct 2012 17:43:41 -0500 > Jesse Barnes wrote: > > > Workaround for a culling optimization. > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ > > 2 files changed, 9 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index c75539b..3ceeb68 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -521,6 +521,7 @@ > > */ > > # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) > > #define _3D_CHICKEN3 0x02090 > > +#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) > > #define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) > > > > #define MI_MODE 0x0209c > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 828629b..400dd05 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3533,6 +3533,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > > > > I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); > > > > + /* WaDisableEarlyCull */ > > + I915_WRITE(_3D_CHICKEN3, > > + _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > > + > > I915_WRITE(IVB_CHICKEN3, > > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > @@ -3611,6 +3615,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > > > I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); > > > > + /* WaDisableEarlyCull */ > > + I915_WRITE(_3D_CHICKEN3, > > + _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > > + > > I915_WRITE(IVB_CHICKEN3, > > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > FYI: We need this for pre-production HSW also (while we have to use > those platforms). > > Reviewed-by: Ben Widawsky Picked up for -fixes, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch