From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Remove the disabling of VHR unit
 clock gating for HSW
Date: Sun, 7 Oct 2012 22:28:04 +0200
Message-ID: <20121007202755.GA7352@phenom.ffwll.local>
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To: Paulo Zanoni <przanoni@gmail.com>
Cc: Damien Lespiau <damien.lespiau@gmail.com>, intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
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On Fri, Oct 05, 2012 at 10:40:35AM -0300, Paulo Zanoni wrote:
> 2012/10/5 Damien Lespiau <damien.lespiau@gmail.com>:
> > From: Damien Lespiau <damien.lespiau@intel.com>
> >
> > There's is another register (a read only, so no harm done) at 0x42020 on
> > Haswell GPUs. Let's just remove the write from the copy&paste that
> > introduced haswell_init_clock_gating().
> >
> > A note for the interested reader, it does seem we have a duplication of
> > the 0x42020 register definition, hence the removal of 2 writes. That
> > duplication could be the object of a later patch.
> >
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Nice catch!
> 
> As you pointed, it seems that we're applying the same workaround twice
> in some functions. You fixed the problem in haswell_init_clock_gating
> by just removing both register writes, but could you also write a new
> patch to fix ivybridge_init_clock_gating and
> valleyview_init_clock_gating to not apply the same workaround twice?
> Maybe just remove the ILK_DSPCLK_GATE definitions and just use
> PCH_DSPCLK_GATE_D everywhere, removing duplicated code? Then we'd also
> have to check ironlake_init_clock_gating and gen6_init_clock_gating...
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch