From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 07/10] drm/i915: completely rewrite the
 Haswell PLL handling code
Date: Wed, 10 Oct 2012 16:52:45 +0200
Message-ID: <20121010145245.GE5533@phenom.ffwll.local>
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To: "Lespiau, Damien" <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Wed, Oct 10, 2012 at 03:22:01PM +0100, Lespiau, Damien wrote:
> On Fri, Oct 5, 2012 at 4:05 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> > +               val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SCC;
> 
> We probably want a patch on top to fix the SCC typo (should be SSC,
> Spread Spectrum Clock).
> 
> There's also some fiddly bit with CPU Vs PCH SSC sources, but this can
> be a later addition.

Hm, I don't understand what PCH SSC resources we have on hsw (which are
not just vga encoder resources, since that's the only pch encoder left).

Two more things I've noticed while reading the patch:
- the simple refcounting seems to be good enough for now, but I guess for
  pll sharing we need a real struct intel_ddi_pll, like for the pch plls.
  But that's likely best done together with the pll readout code required
  for fastboot.

- When will the wrpll table die ... ;-)

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch