From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings
 on gen2
Date: Thu, 11 Oct 2012 10:37:54 +0200
Message-ID: <20121011083754.GA5799@phenom.ffwll.local>
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To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
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On Wed, Oct 10, 2012 at 11:37:36PM +0100, Chris Wilson wrote:
> On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > It doesn't work since the gtt pte range sits in the middle of the mmio
> > bar. We didn't notice that since both my and Chris' gen2 machines
> > don't support PAT and hence all wc io mapping request will
> > automatically be demoted to uc.
> > 
> > This regression has been introduce in
> > 
> > commit edef7e685da05c13cce50c0126189c80fe2c8f71
> > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > Date:   Fri Sep 14 11:57:47 2012 +0100
> > 
> >     agp/intel: Use a write-combining map for updating PTEs
> > 
> > Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Thanks for the explanation,
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Patch merged to -fixes.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch