From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH] drm/i915: flush system agent TLBs on SNB so we can WC map the PTEs Date: Thu, 11 Oct 2012 10:32:37 -0700 Message-ID: <20121011103237.21e6637c@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy12-pub.bluehost.com (oproxy12-pub.bluehost.com [50.87.16.10]) by gabe.freedesktop.org (Postfix) with SMTP id EC2649E982 for ; Thu, 11 Oct 2012 10:31:57 -0700 (PDT) Received: from [67.161.37.189] (port=43383 helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.76) (envelope-from ) id 1TMMc1-0005BJ-H5 for intel-gfx@lists.freedesktop.org; Thu, 11 Oct 2012 11:31:57 -0600 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org I've only lightly tested this so far, but the corruption seems to be gone if I write the GFX_FLSH_CNTL reg after binding an object. This register should control the TLB for the system agent, which is what CPU mapped objects will go through. Signed-off-by: Jesse Barnes diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 6ec0fff..95f0d4d 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h @@ -99,6 +99,9 @@ #define GFX_FLSH_CNTL 0x2170 /* 915+ */ #define GFX_FLSH_CNTL_VLV 0x101008 +#define GFX_FLSH_CNTL 0x101008 +#define GFX_FLSH_CNTL_EN (1<<0) + #define I810_DRAM_CTL 0x3000 #define I810_DRAM_ROW_0 0x00000001 #define I810_DRAM_ROW_0_SDRAM 0x00000001 diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index e01f5ea..08844d6 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -667,12 +667,8 @@ static int intel_gtt_init(void) gtt_map_size = intel_private.base.gtt_total_entries * 4; intel_private.gtt = NULL; - if (INTEL_GTT_GEN < 6) - intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, - gtt_map_size); - if (intel_private.gtt == NULL) - intel_private.gtt = ioremap(intel_private.gtt_bus_addr, - gtt_map_size); + intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, + gtt_map_size); if (intel_private.gtt == NULL) { intel_private.driver->cleanup(); iounmap(intel_private.registers); @@ -897,6 +893,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st, } } readl(intel_private.gtt+j-1); + writel(GFX_FLSH_CNTL_EN, intel_private.registers + GFX_FLSH_CNTL); } EXPORT_SYMBOL(intel_gtt_insert_sg_entries); @@ -913,6 +910,7 @@ static void intel_gtt_insert_pages(unsigned int first_entry, j, flags); } readl(intel_private.gtt+j-1); + writel(GFX_FLSH_CNTL_EN, intel_private.registers + GFX_FLSH_CNTL); } static int intel_fake_agp_insert_entries(struct agp_memory *mem, @@ -1256,7 +1254,7 @@ static int i9xx_setup(void) reg_addr &= 0xfff80000; - if (INTEL_GTT_GEN >= 7) + if (INTEL_GTT_GEN >= 6) size = MB(2); intel_private.registers = ioremap(reg_addr, size);