From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] DRM/i915: Don't delete DPLL Multiplier during DAC init. Date: Tue, 16 Oct 2012 09:33:51 +0200 Message-ID: <20121016073351.GF5753@phenom.ffwll.local> References: <1350225191-8444-1-git-send-email-eich@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EB0E9E78E for ; Tue, 16 Oct 2012 00:32:50 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u50so3720620wey.36 for ; Tue, 16 Oct 2012 00:32:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1350225191-8444-1-git-send-email-eich@suse.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Egbert Eich Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sun, Oct 14, 2012 at 04:33:11PM +0200, Egbert Eich wrote: > The DPLL multipiler is set up in intel_display.c:i9xx_update_pll() > called from i9xx_crtc_mode_set(). > There the DPLL multiplier is adjusted so that the SDVO gets a sufficient > bus clock. > When cloning a CRTC between an SDVO driven encoder and the standard > DAC the DAC setup code reseted the multiplier value to 1 thus undoing > the correct setup. There is no need to touch the multiplier in the DAC > setup code: the correct value (i.e. 1 in case no SDVO encoder is used) > is set by i9xx_update_pll() already. > A comment at the code suggested that this code is a left over from the > days when there was no setup for clone modes. > > Signed-off-by: Egbert Eich Picked up for -fixes, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch